From patchwork Tue Oct 6 12:09:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 526717 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8E88F140D68 for ; Tue, 6 Oct 2015 23:10:11 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=dQgcNyEB; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=DcAK6my6WQHN/1P5G ataewomHc48TVoPJUD80nCj/FbayafVFQ9FIRM/0EzlNJuzlL5m8d9gS41kprJYM YumEtAx4GIFNriguJVfLS7Q6GwEL4WNUGJImOOMq2H6pMIui1FyJ3/TITzj8CmAE BcaAwU90krI80F3wM+VKIt+Lrw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=R81ryhLOgvNxM0Qj19vuP0x cXFk=; b=dQgcNyEBMyRekavTWQ2gp+dxTRyl6FLyYHjoWmY4UZ+LaHfbKO1hKwf fJ7xuEFq7Av0pqZpypCN2hUivL+hO4Ve3E10Kgs/DmDGMYAz0kpFvubEXn2qGXi0 g9VZdok2/pnS78ZtGPt9NWBP+2UOFC+lixO50vRWqB7Yw195LuoE= Received: (qmail 61622 invoked by alias); 6 Oct 2015 12:10:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 58868 invoked by uid 89); 6 Oct 2015 12:10:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-io0-f196.google.com Received: from mail-io0-f196.google.com (HELO mail-io0-f196.google.com) (209.85.223.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 06 Oct 2015 12:10:01 +0000 Received: by iow1 with SMTP id 1so18109796iow.1 for ; Tue, 06 Oct 2015 05:09:59 -0700 (PDT) X-Received: by 10.107.47.221 with SMTP id v90mr32433713iov.185.1444133399510; Tue, 06 Oct 2015 05:09:59 -0700 (PDT) Received: from msticlxl57.ims.intel.com (jfdmzpr02-ext.jf.intel.com. [134.134.137.71]) by smtp.gmail.com with ESMTPSA id e8sm6675691igx.16.2015.10.06.05.09.56 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Oct 2015 05:09:58 -0700 (PDT) Date: Tue, 6 Oct 2015 15:09:40 +0300 From: Kirill Yukhin To: "H.J. Lu" Cc: Uros Bizjak , GCC Patches Subject: Re: [PATCH, i386, AVX-512] Update extract_even_odd w/ AVX-512BW insns. Message-ID: <20151006120937.GD56984@msticlxl57.ims.intel.com> References: <20151001111155.GA17847@msticlxl57.ims.intel.com> <20151002143741.GC5228@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes > > This caused: > > > > FAIL: gcc.target/i386/vect-perm-odd-1.c (test for excess errors) > > > > on gcc-5-branch. > > > > vect-perm-odd-1.s: Assembler messages: > vect-perm-odd-1.s:233: Error: operand type mismatch for `vpor' > vect-perm-odd-1.s:240: Error: operand type mismatch for `vpor' > > vpor %zmm1, %zmm2, %zmm1 > > It should be > > vporq %zmm1, %zmm2, %zmm1 It looks like patch revealed issue w/ wrong `or' emit. Patch of Alexander Fomin fixes it. I've backported it for gcc-5. Bootstrapped. Regtest in progress. Is it ok for gcc-5 if regtesting pass? (plan B is to revert causing commit from gcc-5) --- Thanks, K commit 6fb351df5ddc144a9a487b70bd9945d1e21a0033 Author: kyukhin Date: Tue Sep 22 11:14:25 2015 +0000 PR target/67480 gcc/ * config/i386/sse.md (define_mode_iterator VI48_AVX_AVX512F): New. (define_mode_iterator VI12_AVX_AVX512F): New. (define_insn "3"): Change all iterators to VI48_AVX_AVX512F. Extract remaining modes ... (define_insn "*3"): ... Into new pattern using VI12_AVX_AVX512F iterators without masking. gcc/testsuite/ * gcc.target/i386/pr67480.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228010 138bc75d-0d04-0410-961f-82ee72b054a4 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 7134b02..dc7f6a7 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -410,6 +410,14 @@ [(V16SI "TARGET_AVX512F") V8SI V4SI (V8DI "TARGET_AVX512F") V4DI V2DI]) +(define_mode_iterator VI48_AVX_AVX512F + [(V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI + (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI]) + +(define_mode_iterator VI12_AVX_AVX512F + [ (V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI + (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI]) + (define_mode_iterator V48_AVX2 [V4SF V2DF V8SF V4DF @@ -10917,10 +10925,10 @@ }) (define_insn "3" - [(set (match_operand:VI 0 "register_operand" "=x,v") - (any_logic:VI - (match_operand:VI 1 "nonimmediate_operand" "%0,v") - (match_operand:VI 2 "nonimmediate_operand" "xm,vm")))] + [(set (match_operand:VI48_AVX_AVX512F 0 "register_operand" "=x,v") + (any_logic:VI48_AVX_AVX512F + (match_operand:VI48_AVX_AVX512F 1 "nonimmediate_operand" "%0,v") + (match_operand:VI48_AVX_AVX512F 2 "nonimmediate_operand" "xm,vm")))] "TARGET_SSE && && ix86_binary_operator_ok (, mode, operands)" { @@ -10949,24 +10957,120 @@ case V4DImode: case V4SImode: case V2DImode: - if (TARGET_AVX512VL) + tmp = TARGET_AVX512VL ? "p" : "p"; + break; + default: + gcc_unreachable (); + } + break; + + case MODE_V8SF: + gcc_assert (TARGET_AVX); + case MODE_V4SF: + gcc_assert (TARGET_SSE); + gcc_assert (!); + tmp = "ps"; + break; + + default: + gcc_unreachable (); + } + + switch (which_alternative) + { + case 0: + if () + ops = "v%s\t{%%2, %%0, %%0|%%0, %%0, %%2}"; + else + ops = "%s\t{%%2, %%0|%%0, %%2}"; + break; + case 1: + ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + break; + default: + gcc_unreachable (); + } + + snprintf (buf, sizeof (buf), ops, tmp); + return buf; +} + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog") + (set (attr "prefix_data16") + (if_then_else + (and (eq_attr "alternative" "0") + (eq_attr "mode" "TI")) + (const_string "1") + (const_string "*"))) + (set_attr "prefix" "") + (set (attr "mode") + (cond [(and (match_test " == 16") + (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")) + (const_string "") + (match_test "TARGET_AVX2") + (const_string "") + (match_test "TARGET_AVX") + (if_then_else + (match_test " > 16") + (const_string "V8SF") + (const_string "")) + (ior (not (match_test "TARGET_SSE2")) + (match_test "optimize_function_for_size_p (cfun)")) + (const_string "V4SF") + ] + (const_string "")))]) + +(define_insn "*3" + [(set (match_operand:VI12_AVX_AVX512F 0 "register_operand" "=x,v") + (any_logic: VI12_AVX_AVX512F + (match_operand:VI12_AVX_AVX512F 1 "nonimmediate_operand" "%0,v") + (match_operand:VI12_AVX_AVX512F 2 "nonimmediate_operand" "xm,vm")))] + "TARGET_SSE && ix86_binary_operator_ok (, mode, operands)" +{ + static char buf[64]; + const char *ops; + const char *tmp; + const char *ssesuffix; + + switch (get_attr_mode (insn)) + { + case MODE_XI: + gcc_assert (TARGET_AVX512F); + case MODE_OI: + gcc_assert (TARGET_AVX2 || TARGET_AVX512VL); + case MODE_TI: + gcc_assert (TARGET_SSE2 || TARGET_AVX512VL); + switch (mode) + { + case V64QImode: + case V32HImode: + if (TARGET_AVX512F) { - tmp = "p"; + tmp = "p"; + ssesuffix = "q"; + break; + } + case V32QImode: + case V16HImode: + case V16QImode: + case V8HImode: + if (TARGET_AVX512VL || TARGET_AVX2 || TARGET_SSE2) + { + tmp = "p"; + ssesuffix = TARGET_AVX512VL ? "q" : ""; break; } default: - tmp = TARGET_AVX512VL ? "pq" : "p"; + gcc_unreachable (); } break; - case MODE_V16SF: - gcc_assert (TARGET_AVX512F); case MODE_V8SF: gcc_assert (TARGET_AVX); case MODE_V4SF: gcc_assert (TARGET_SSE); - tmp = "ps"; + ssesuffix = ""; break; default: @@ -10977,15 +11081,16 @@ { case 0: ops = "%s\t{%%2, %%0|%%0, %%2}"; + snprintf (buf, sizeof (buf), ops, tmp); break; case 1: - ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + ops = "v%s%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + snprintf (buf, sizeof (buf), ops, tmp, ssesuffix); break; default: gcc_unreachable (); } - snprintf (buf, sizeof (buf), ops, tmp); return buf; } [(set_attr "isa" "noavx,avx") diff --git a/gcc/testsuite/gcc.target/i386/pr67480.c b/gcc/testsuite/gcc.target/i386/pr67480.c new file mode 100644 index 0000000..90e6a6e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67480.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512bw -O2 -ftree-vectorize" { target i?86-*-* x86_64-*-* } } */ + +void +foo(const char *in, char *out, unsigned n) +{ + unsigned i; + for (i = 0; i < n; i++) + out[i] &= in[i]; +}