From patchwork Tue Oct 6 07:24:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 526632 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 68B78140D9B for ; Tue, 6 Oct 2015 18:24:55 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=B5Zu5foU; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=Yhu2hr9zcMhNrT+qG 4mNch3s60njk/uaMFG+ean1ZYkQnyWCDZT6j5snmmgAIySUblvmsgvSRyZNpqCv4 TNWS4ARRW0gmXB4d9sK4sJZk4R6q3fRZCpLglX2jCThjn4hCEepGYGwzjX6EwK04 dMwVA91utj7++mZa58D3oN/AYU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=CuoZNBPlCnbhHQusqtLEzVf 3Ff8=; b=B5Zu5foU7vnycr+aJCGpx5RfztfVAvtNAkwpLeBu7U8rmaFA4DF0/Ho 6Z/O80ZWn8YA4ALNSQ2a4xyAW2S7d4wXGQlc6mVY58oet8/8iCiejT2vDyvvZx9l 4cnoSStZ0tcnO1RhsWd753chrICQ5LBB7IDgc0rRQv5bQfi60EmA= Received: (qmail 99275 invoked by alias); 6 Oct 2015 07:24:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 98710 invoked by uid 89); 6 Oct 2015 07:24:33 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qk0-f170.google.com Received: from mail-qk0-f170.google.com (HELO mail-qk0-f170.google.com) (209.85.220.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 06 Oct 2015 07:24:32 +0000 Received: by qkbi190 with SMTP id i190so61161522qkb.1 for ; Tue, 06 Oct 2015 00:24:30 -0700 (PDT) X-Received: by 10.55.24.6 with SMTP id j6mr24222182qkh.93.1444116270187; Tue, 06 Oct 2015 00:24:30 -0700 (PDT) Received: from msticlxl57.ims.intel.com (jfdmzpr02-ext.jf.intel.com. [134.134.137.71]) by smtp.gmail.com with ESMTPSA id g49sm13265216qgg.10.2015.10.06.00.24.26 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Oct 2015 00:24:29 -0700 (PDT) Date: Tue, 6 Oct 2015 10:24:06 +0300 From: Kirill Yukhin To: Uros Bizjak Cc: Jakub Jelinek , GCC Patches Subject: Re: [PATCH, i386] Introduce switch for Skylake Server CPU. Message-ID: <20151006072402.GA56984@msticlxl57.ims.intel.com> References: <20150921141442.GD49423@msticlxl57.ims.intel.com> <20150921142728.GB1847@tucnak.redhat.com> <20150921165719.GA14053@msticlxl57.ims.intel.com> <20150922093120.GA10287@msticlxl57.ims.intel.com> <20151002161215.GF5228@msticlxl57.ims.intel.com> <20151006070951.GC62312@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20151006070951.GC62312@msticlxl57.ims.intel.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes One more missed hunk: iff --git a/gcc/testsuite/gcc.target/i386/builtin_target.c b/gcc/testsuite/gcc.target/i386/builtin_target.c index 9eb397e..cbca6b4 100644 --- a/gcc/testsuite/gcc.target/i386/builtin_target.c +++ b/gcc/testsuite/gcc.target/i386/builtin_target.c @@ -173,6 +173,10 @@ check_features (unsigned int ecx, unsigned int edx, assert (__builtin_cpu_supports ("sse2")); if (ecx & bit_POPCNT) assert (__builtin_cpu_supports ("popcnt")); + if (ecx & bit_AES) + assert (__builtin_cpu_supports ("aes")); + if (ecx & bit_PCLMUL) + assert (__builtin_cpu_supports ("pclmul")); if (ecx & bit_SSE3) assert (__builtin_cpu_supports ("sse3")); if (ecx & bit_SSSE3)