From patchwork Thu Aug 20 21:15:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 509170 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8AF9E1402C8 for ; Fri, 21 Aug 2015 07:15:41 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=CXLvCt6s; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; q=dns; s= default; b=HnKtx5Z3Sm3m95IYu6UJT7KeXpHtftpZmxuAuLQJV3k3ZYD7VCn1S EEbXr/huu+H/YiF8XU3B4FL0Cb0gPzAOhM0AQSq9ZHsK+jnYEfUWRoQtTXPBIBKP a/LR05hI6txUeihG1MWWidIJDjNHp7Wnij3QpYLMEZdw3oYSKx5J6I= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; s= default; bh=nW0t4gaPYrBF3TdfSndlVHat6HQ=; b=CXLvCt6ssIFR25TDECPC HACGtqEtsbjNMQKqGS/0uL+xptKb/8DeA/yxeYeM9NrRlZt0Vst8kZaBMQMsc6PI 3IJRXwIbgh3gayD9k9I2U0A6NrcL3mYP7zhHijzE8ytHNEcbaKCBxlmex+4e3yYw VNmEetMvqnUMINO/Vxkcipk= Received: (qmail 127117 invoked by alias); 20 Aug 2015 21:15:28 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 127108 invoked by uid 89); 20 Aug 2015 21:15:27 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.5 required=5.0 tests=AWL, BAYES_00, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY autolearn=no version=3.3.2 X-HELO: e37.co.us.ibm.com Received: from e37.co.us.ibm.com (HELO e37.co.us.ibm.com) (32.97.110.158) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Thu, 20 Aug 2015 21:15:25 +0000 Received: from /spool/local by e37.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 20 Aug 2015 15:15:21 -0600 X-MailFrom: meissner@ibm-tiger.the-meissners.org X-RcptTo: gcc-patches@gcc.gnu.org Received: from b03cxnp07028.gho.boulder.ibm.com (b03cxnp07028.gho.boulder.ibm.com [9.17.130.15]) by d03dlp01.boulder.ibm.com (Postfix) with ESMTP id D85481FF004C for ; Thu, 20 Aug 2015 15:06:30 -0600 (MDT) Received: from d03av05.boulder.ibm.com (d03av05.boulder.ibm.com [9.17.195.85]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t7KLCWk226017872 for ; Thu, 20 Aug 2015 14:12:32 -0700 Received: from d03av05.boulder.ibm.com (localhost [127.0.0.1]) by d03av05.boulder.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t7KLFKc0011136 for ; Thu, 20 Aug 2015 15:15:20 -0600 Received: from ibm-tiger.the-meissners.org (dhcp-9-32-77-111.usma.ibm.com [9.32.77.111]) by d03av05.boulder.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t7KLFJKc011011; Thu, 20 Aug 2015 15:15:19 -0600 Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 2F03442C85; Thu, 20 Aug 2015 17:15:18 -0400 (EDT) Date: Thu, 20 Aug 2015 17:15:18 -0400 From: Michael Meissner To: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com Subject: [PATCH], PR target/67211, Fix PowerPC 'insn does not satisfy its constraints' error on GCC 5 Message-ID: <20150820211518.GA11427@ibm-tiger.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15082021-0025-0000-0000-00001A47030E X-IsSubscribed: yes PR 67211 is an error that shows up on the GCC 5.x branch when the test case is compiled with -mcpu=power7 -mtune=power8 -O3. In looking at the code, I noticed that the code optimized adjancent 64-bit integer/pointers in a structure from DImode to V2DImode. The compiler optimized these to the vector registers, and then tried to move a common field used later back to the GPR field. If the cpu was power8, it would be able to use the direct move instructions, but on power7 those instructions don't exist. The current trunk compiler has dialed back on the optimization, and it no longer tries to optimize adjacent fields in this particular case to V2DImode, but it is an issue in the GCC 5 branch. In debugging the issue, I noticed the -mefficient-unaligned-VSX option was being set if -mtune=power8 was used, even if the architecture was not a power8. Efficient unaligned VSX is an architecture feature, and not a tuning feature. In fixing this to be an architecture feature, it no longer tried to do the V2DImode optimization because it didn't have fast unaligned support. I have checked this on a big endian power7 and a little endian power8 system, using the GCC 5.x patches and the patches for the trunk. There were no regressions in any of the runs. Is it ok to install these patches on both the GCC 5.x branch and trunk? I would like to commit a similar patch for the 4.9 branch as well. Is this ok? Note, due to rs6000.opt being slightly different between GCC 5.x and trunk, there are two different patches, one for GCC 5.x and the other for GCC 6.x (trunk). [gcc] 2015-08-20 Michael Meissner PR target/67211 * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Set -mefficient-unaligned-vsx on ISA 2.7. * config/rs6000/rs6000.opt (-mefficient-unaligned-vsx): Convert option to a masked option. * config/rs6000/rs6000.c (rs6000_option_override_internal): Rework logic for -mefficient-unaligned-vsx so that it is set via an arch ISA option, instead of being set if -mtune=power8 is set. Move -mefficient-unaligned-vsx and -mallow-movmisalign handling to be near other default option handling. [gcc/testsuite] 2015-08-20 Michael Meissner PR target/67211 * g++.dg/pr67211.C: New test. Index: gcc/config/rs6000/rs6000-cpus.def =================================================================== --- gcc/config/rs6000/rs6000-cpus.def (revision 226986) +++ gcc/config/rs6000/rs6000-cpus.def (working copy) @@ -53,6 +53,7 @@ | OPTION_MASK_P8_VECTOR \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DIRECT_MOVE \ + | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_HTM \ | OPTION_MASK_QUAD_MEMORY \ | OPTION_MASK_QUAD_MEMORY_ATOMIC \ @@ -78,6 +79,7 @@ | OPTION_MASK_DFP \ | OPTION_MASK_DIRECT_MOVE \ | OPTION_MASK_DLMZB \ + | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FPRND \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ Index: gcc/config/rs6000/rs6000.opt =================================================================== --- gcc/config/rs6000/rs6000.opt (revision 226986) +++ gcc/config/rs6000/rs6000.opt (working copy) @@ -212,7 +212,7 @@ Target Undocumented Var(TARGET_ALLOW_MOV ; Allow/disallow the movmisalign in DF/DI vectors mefficient-unaligned-vector -Target Undocumented Report Var(TARGET_EFFICIENT_UNALIGNED_VSX) Init(-1) Save +Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags) ; Consider unaligned VSX accesses to be efficient/inefficient mallow-df-permute Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 226986) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -3692,6 +3692,45 @@ rs6000_option_override_internal (bool gl && optimize >= 3) rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN; + /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07 + support. If we only have ISA 2.06 support, and the user did not specify + the switch, leave it set to -1 so the movmisalign patterns are enabled, + but we don't enable the full vectorization support */ + if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE) + TARGET_ALLOW_MOVMISALIGN = 1; + + else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX) + { + if (TARGET_ALLOW_MOVMISALIGN > 0) + error ("-mallow-movmisalign requires -mvsx"); + + TARGET_ALLOW_MOVMISALIGN = 0; + } + + /* Determine when unaligned vector accesses are permitted, and when + they are preferred over masked Altivec loads. Note that if + TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then + TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is + not true. */ + if (TARGET_EFFICIENT_UNALIGNED_VSX) + { + if (!TARGET_VSX) + { + if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX) + error ("-mefficient-unaligned-vsx requires -mvsx"); + + rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX; + } + + else if (!TARGET_ALLOW_MOVMISALIGN) + { + if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX) + error ("-mefficient-unaligned-vsx requires -mallow-movmisalign"); + + rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX; + } + } + if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags); @@ -4251,22 +4290,6 @@ rs6000_option_override_internal (bool gl } } - /* Determine when unaligned vector accesses are permitted, and when - they are preferred over masked Altivec loads. Note that if - TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then - TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is - not true. */ - if (TARGET_EFFICIENT_UNALIGNED_VSX == -1) { - if (TARGET_VSX && rs6000_cpu == PROCESSOR_POWER8 - && TARGET_ALLOW_MOVMISALIGN != 0) - TARGET_EFFICIENT_UNALIGNED_VSX = 1; - else - TARGET_EFFICIENT_UNALIGNED_VSX = 0; - } - - if (TARGET_ALLOW_MOVMISALIGN == -1 && rs6000_cpu == PROCESSOR_POWER8) - TARGET_ALLOW_MOVMISALIGN = 1; - /* Set the builtin mask of the various options used that could affect which builtins were used. In the past we used target_flags, but we've run out of bits, and some options like SPE and PAIRED are no longer in @@ -32280,6 +32303,8 @@ static struct rs6000_opt_mask const rs60 { "crypto", OPTION_MASK_CRYPTO, false, true }, { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true }, { "dlmzb", OPTION_MASK_DLMZB, false, true }, + { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX, + false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, { "hard-dfp", OPTION_MASK_DFP, false, true }, { "htm", OPTION_MASK_HTM, false, true }, Index: gcc/testsuite/g++.dg/pr67211.C =================================================================== --- gcc/testsuite/g++.dg/pr67211.C (revision 0) +++ gcc/testsuite/g++.dg/pr67211.C (revision 0) @@ -0,0 +1,50 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-options "-mcpu=power7 -mtune=power8 -O3 -w" } */ + +/* target/67211, compiler got a 'insn does not satisfy its constraints' error. */ + +template +void find_first_of(_InputIterator, _InputIterator, _ForwardIterator p3, + _ForwardIterator p4) { + for (; p3 != p4; ++p3) + ; +} + +template struct A { + int _S_buffer_size; + int *_M_cur; + int *_M_first; + int *_M_last; + int **_M_node; + void operator++() { + if (_M_cur == _M_last) + m_fn1(_M_node + 1); + } + void m_fn1(int **p1) { + _M_node = p1; + _M_first = *p1; + _M_last = _M_first + _S_buffer_size; + } +}; + +template +bool operator==(A<_Tp, _Ref, _Ptr>, A<_Tp, _Ref, _Ptr>); +template +bool operator!=(A<_Tp, _Ref, _Ptr> p1, A<_Tp, _Ref, _Ptr> p2) { + return p1 == p2; +} + +class B { +public: + A m_fn2(); +}; +struct { + B j; +} a; +void Linked() { + A b, c, d; + find_first_of(d, c, b, a.j.m_fn2()); +}