diff mbox

[Committed] S/390: Clobber VRs in __builtin_tbegin

Message ID 20150806103301.GA1984@maggie
State New
Headers show

Commit Message

Andreas Krebbel Aug. 6, 2015, 10:33 a.m. UTC 
Hi,

a transaction rollback does not restore the contents of vector
registers.  So we have to add clobbers for them as we are doing
already for the FPRs.

Bootstrap and regression testing is fine on z13, zEC12, and z196 with
31 and 64 bit.

Committed to mainline.

Bye,

-Andreas-

gcc/ChangeLog:

2015-08-06  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/s390.c (s390_expand_tbegin): Expand either
	tbegin_1_z13 or tbegin_1 depending on VX flag.
	* config/s390/s390.md ("tbegin_1_z13"): New expander.

gcc/testsuite/ChangeLog:

2015-08-06  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* gcc.target/s390/htm-builtins-z13-1.c: New test.
diff mbox

Patch

diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index e10da7a..c529f56 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -11651,7 +11651,14 @@  s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p)
     }
 
   if (clobber_fprs_p)
-    emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb));
+    {
+      if (TARGET_VX)
+	emit_insn (gen_tbegin_1_z13 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK),
+				     tdb));
+      else
+	emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK),
+				 tdb));
+    }
   else
     emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK),
 				     tdb));
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 959ca8cb..b738989 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -10639,6 +10639,35 @@ 
   DONE;
 })
 
+; Clobber VRs since they don't get restored
+(define_insn "tbegin_1_z13"
+  [(set (reg:CCRAW CC_REGNUM)
+	(unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
+			       UNSPECV_TBEGIN))
+   (set (match_operand:BLK 1 "memory_operand" "=Q")
+	(unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
+   (clobber (reg:TI 16)) (clobber (reg:TI 38))
+   (clobber (reg:TI 17)) (clobber (reg:TI 39))
+   (clobber (reg:TI 18)) (clobber (reg:TI 40))
+   (clobber (reg:TI 19)) (clobber (reg:TI 41))
+   (clobber (reg:TI 20)) (clobber (reg:TI 42))
+   (clobber (reg:TI 21)) (clobber (reg:TI 43))
+   (clobber (reg:TI 22)) (clobber (reg:TI 44))
+   (clobber (reg:TI 23)) (clobber (reg:TI 45))
+   (clobber (reg:TI 24)) (clobber (reg:TI 46))
+   (clobber (reg:TI 25)) (clobber (reg:TI 47))
+   (clobber (reg:TI 26)) (clobber (reg:TI 48))
+   (clobber (reg:TI 27)) (clobber (reg:TI 49))
+   (clobber (reg:TI 28)) (clobber (reg:TI 50))
+   (clobber (reg:TI 29)) (clobber (reg:TI 51))
+   (clobber (reg:TI 30)) (clobber (reg:TI 52))
+   (clobber (reg:TI 31)) (clobber (reg:TI 53))]
+; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
+; not supposed to be used for immediates (see genpreds.c).
+  "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
+  "tbegin\t%1,%x0"
+  [(set_attr "op_type" "SIL")])
+
 (define_insn "tbegin_1"
   [(set (reg:CCRAW CC_REGNUM)
 	(unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
diff --git a/gcc/testsuite/gcc.target/s390/htm-builtins-z13-1.c b/gcc/testsuite/gcc.target/s390/htm-builtins-z13-1.c
new file mode 100644
index 0000000..7879c36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/htm-builtins-z13-1.c
@@ -0,0 +1,34 @@ 
+/* Verify if VRs are saved and restored.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target vector } */
+/* { dg-options "-O3 -march=z13 -mzarch" } */
+
+typedef int __attribute__((vector_size(16))) v4si;
+
+v4si __attribute__((noinline))
+foo (v4si a)
+{
+  a += (v4si){ 1, 1, 1, 1 };
+  if (__builtin_tbegin (0) == 0)
+    {
+      a += (v4si){ 1, 1, 1, 1 };
+      __builtin_tabort (256);
+      __builtin_tend ();
+    }
+  else
+    a -= (v4si){ 1, 1, 1, 1 };
+
+  return a;
+}
+
+int
+main ()
+{
+  v4si a = (v4si){ 0, 0, 0, 0 };
+
+  a = foo (a);
+
+  if (a[0] != 0)
+    __builtin_abort ();
+}