From patchwork Tue Aug 4 12:33:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 503578 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8F65A1402E2 for ; Tue, 4 Aug 2015 22:33:33 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=dyHN0Mop; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=o1ODK2h22I7c+mLbO 88FVXGDTx2dDv7voJUw5THeCGepvKgCLGlXCiUMdgZ6fhstWKcccX9W3adA1E1xx SV9Rncmjq7kwJROSpKIn9ABTic59AT6W7fhNTpZgdP62hxVbKcww9laP+F6gPWW4 K8326jOnLvl4WnrkjfgBJrAves= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=xNXK5Ox8nT4TOGGvvyv4W98 RqjU=; b=dyHN0MopO48zqv7snRMAG4SAbENmmtvGWMoT182hozqTr6A5c8j428c WqNP6P7lo/rH3+SUBY0nodIg7t9AnRhEU6xCv3U14o8fnAj9xTIRlJ2Hqa0aT+cA VUHPqGEBu4DgsmoWWt8pgaFaRABeM+BIS8ikYHO6XNM2uTsiWJUc= Received: (qmail 130086 invoked by alias); 4 Aug 2015 12:33:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 130069 invoked by uid 89); 4 Aug 2015 12:33:26 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qk0-f182.google.com Received: from mail-qk0-f182.google.com (HELO mail-qk0-f182.google.com) (209.85.220.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 04 Aug 2015 12:33:16 +0000 Received: by qkdv3 with SMTP id v3so2399387qkd.3 for ; Tue, 04 Aug 2015 05:33:14 -0700 (PDT) X-Received: by 10.55.23.95 with SMTP id i92mr5944553qkh.30.1438691594103; Tue, 04 Aug 2015 05:33:14 -0700 (PDT) Received: from msticlxl57.ims.intel.com (fmdmzpr04-ext.fm.intel.com. [192.55.55.39]) by smtp.gmail.com with ESMTPSA id l125sm384178qhl.15.2015.08.04.05.33.11 (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Aug 2015 05:33:13 -0700 (PDT) Date: Tue, 4 Aug 2015 15:33:04 +0300 From: Kirill Yukhin To: Uros Bizjak Cc: GCC Patches Subject: Re: [PATCH, i386] Merge SSE and AVX ptest patterns. Message-ID: <20150804123302.GD32256@msticlxl57.ims.intel.com> References: <20150804115838.GB32256@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes On 04 Aug 14:06, Uros Bizjak wrote: > On Tue, Aug 4, 2015 at 1:58 PM, Kirill Yukhin wrote: > > + (set (attr "btver2_decode") > > + (if_then_else > > + (and (eq_attr "alternative" "2") > > + (match_test "mode==OImode")) > > + (const_string "vector") > > + (const_string "*"))) > > "vector" does not depend on alternative, but only on > mode. So the and above should be removed. Thanks, fixed! > Uros. commit 20df38ce6fed082155b9860b0a1c5511894fdd84 Author: Kirill Yukhin Date: Tue Aug 4 10:36:10 2015 +0300 Merge SSE 4.1 and AVX ptest patterns. Extend iterator for new one. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 128c5af..f93a5ce 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -31734,9 +31734,9 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF }, { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF }, - { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST }, - { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST }, - { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST }, + { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST }, + { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST }, + { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST }, /* SSE4.2 */ { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI }, @@ -31892,9 +31892,9 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST }, - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST }, - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST }, - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST }, + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST }, + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST }, + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF }, diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 0970f0e..0ffc27d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -299,6 +299,12 @@ V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) ;; All DImode vector integer modes +(define_mode_iterator V_AVX + [V16QI V8HI V4SI V2DI V4SF V2DF + (V32QI "TARGET_AVX") (V16HI "TARGET_AVX") + (V8SI "TARGET_AVX") (V4DI "TARGET_AVX") + (V8SF "TARGET_AVX") (V4DF"TARGET_AVX")]) + (define_mode_iterator VI8 [(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI]) @@ -566,7 +572,11 @@ (define_mode_attr sse4_1 [(V4SF "sse4_1") (V2DF "sse4_1") (V8SF "avx") (V4DF "avx") - (V8DF "avx512f")]) + (V8DF "avx512f") + (V4DI "avx") (V2DI "sse4_1") + (V8SI "avx") (V4SI "sse4_1") + (V16QI "sse4_1") (V32QI "avx") + (V8HI "sse4_1") (V16HI "avx")]) (define_mode_attr avxsizesuffix [(V64QI "512") (V32HI "512") (V16SI "512") (V8DI "512") @@ -14640,30 +14650,23 @@ ;; ptest is very similar to comiss and ucomiss when setting FLAGS_REG. ;; But it is not a really compare instruction. -(define_insn "avx_ptest256" - [(set (reg:CC FLAGS_REG) - (unspec:CC [(match_operand:V4DI 0 "register_operand" "x") - (match_operand:V4DI 1 "nonimmediate_operand" "xm")] - UNSPEC_PTEST))] - "TARGET_AVX" - "vptest\t{%1, %0|%0, %1}" - [(set_attr "type" "ssecomi") - (set_attr "prefix_extra" "1") - (set_attr "prefix" "vex") - (set_attr "btver2_decode" "vector") - (set_attr "mode" "OI")]) - -(define_insn "sse4_1_ptest" +(define_insn "_ptest" [(set (reg:CC FLAGS_REG) - (unspec:CC [(match_operand:V2DI 0 "register_operand" "Yr,*x") - (match_operand:V2DI 1 "nonimmediate_operand" "Yrm,*xm")] + (unspec:CC [(match_operand:V_AVX 0 "register_operand" "Yr, *x, x") + (match_operand:V_AVX 1 "nonimmediate_operand" "Yrm, *xm, xm")] UNSPEC_PTEST))] "TARGET_SSE4_1" "%vptest\t{%1, %0|%0, %1}" - [(set_attr "type" "ssecomi") + [(set_attr "isa" "*,*,avx") + (set_attr "type" "ssecomi") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") - (set_attr "mode" "TI")]) + (set (attr "btver2_decode") + (if_then_else + (match_test "mode==OImode") + (const_string "vector") + (const_string "*"))) + (set_attr "mode" "")]) (define_insn "_round" [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x")