From patchwork Tue Aug 4 11:47:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 503555 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D7CB51402DD for ; Tue, 4 Aug 2015 21:47:59 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=rK1a1tG9; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=SzjzP5TpkZzzdat1 aivIJ4+LPES6Lh/O1TdDlHWrINGeVlBRgWQzViZwDdZb7N5CLwkRQICPRR0X5xDw pTGnr1tztFhIQ68nNtCZYORO+4pps7YX8BkQ9HtQQeIYER2n1vNVOFpfrvzPylQT MOo645gdz9sJp2EgWAf9URW/4HI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=5W+EmzVJnFWr5zS8A2t+WJ XzWwk=; b=rK1a1tG9/PJcL20diKTUs3SV2pQLSQzQi8tUq0bORQyB3vFAO8YRyT Sg0UvgJyp3MH5Z7dSiaTa1dM127MCac8xa4wBfdVe1n4QRremlecSEYfXmLyKk4/ kDxK0MJ9BQSewMYs4qbjjXSSQwxMKZJ6TgCFOw+Kx3MD2uS7cnoaY= Received: (qmail 17965 invoked by alias); 4 Aug 2015 11:47:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 17955 invoked by uid 89); 4 Aug 2015 11:47:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL, BAYES_20, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-io0-f173.google.com Received: from mail-io0-f173.google.com (HELO mail-io0-f173.google.com) (209.85.223.173) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 04 Aug 2015 11:47:49 +0000 Received: by ioea135 with SMTP id a135so13889746ioe.1 for ; Tue, 04 Aug 2015 04:47:47 -0700 (PDT) X-Received: by 10.107.160.2 with SMTP id j2mr3164286ioe.127.1438688867799; Tue, 04 Aug 2015 04:47:47 -0700 (PDT) Received: from msticlxl57.ims.intel.com (fmdmzpr04-ext.fm.intel.com. [192.55.55.39]) by smtp.gmail.com with ESMTPSA id j83sm1364465iod.25.2015.08.04.04.47.45 (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Aug 2015 04:47:47 -0700 (PDT) Date: Tue, 4 Aug 2015 14:47:37 +0300 From: Kirill Yukhin To: GCC Patches Cc: Uros Bizjak Subject: [PATCH, i386] Disable AVX-512VL insns for scalar mode operands on -march=knl. Message-ID: <20150804114734.GA32256@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Hello, For vec_dup and vec_concat patterns (of v2df mode) second operand is of scalar mode, so `ix86_hard_regno_mode_ok’ didn’t block EVEX registers, of non-512b modes (when AVX-512VL is turned off). This turns into 128/256b xmm[>15] regs emit on -march=knl. There’re should be more patterns w/ similar issue. Will look for them later. Bootstrapped and regtested. If no objections, I'll commit it tomorrow morning (Moscow time). gcc/ * config/i386/i386.md (define_attr "isa"): Addd avx512vl and noavx512vl. (define_attr "enabled"): Handle avx521vl and noavx512vl. * config/i386/sse.md (define_insn "vec_dupv2df"): Split AVX-512 alternative out of SSE. (define_insn "*vec_concatv2df"): Ditto. --- Thanks, K commit 924990a6e8d38b6ebff9dd9a79e285ef81890202 Author: Kirill Yukhin Date: Mon Aug 3 15:21:06 2015 +0300 Fix vec_concatv2df and vec_dupv2df to block wrongly enabled AVX-512VL insns. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 5c5c1fc..9ffe9aa 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -784,7 +784,8 @@ (define_attr "isa" "base,x64,x64_sse4,x64_sse4_noavx,x64_avx,nox64, sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx, avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f, - fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq" + fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq, + avx512vl,noavx512vl" (const_string "base")) (define_attr "enabled" "" @@ -819,6 +820,8 @@ (eq_attr "isa" "noavx512bw") (symbol_ref "!TARGET_AVX512BW") (eq_attr "isa" "avx512dq") (symbol_ref "TARGET_AVX512DQ") (eq_attr "isa" "noavx512dq") (symbol_ref "!TARGET_AVX512DQ") + (eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL") + (eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL") ] (const_int 1))) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 0970f0e..a509369 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -8638,44 +8638,47 @@ (set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")]) (define_insn "vec_dupv2df" - [(set (match_operand:V2DF 0 "register_operand" "=x,v") + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v") (vec_duplicate:V2DF - (match_operand:DF 1 "nonimmediate_operand" " 0,vm")))] + (match_operand:DF 1 "nonimmediate_operand" " 0,xm,vm")))] "TARGET_SSE2 && " "@ unpcklpd\t%0, %0 - %vmovddup\t{%1, %0|%0, %1}" - [(set_attr "isa" "noavx,sse3") + %vmovddup\t{%1, %0|%0, %1} + vmovddup\t{%1, %0|%0, %1}" + [(set_attr "isa" "noavx,sse3,avx512vl") (set_attr "type" "sselog1") - (set_attr "prefix" "orig,maybe_vex") - (set_attr "mode" "V2DF,DF")]) + (set_attr "prefix" "orig,maybe_vex,evex") + (set_attr "mode" "V2DF,DF,DF")]) (define_insn "*vec_concatv2df" - [(set (match_operand:V2DF 0 "register_operand" "=x,v,v,x,x,v,x,x") + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,v,x,x,v,x,x") (vec_concat:V2DF - (match_operand:DF 1 "nonimmediate_operand" " 0,v,m,0,x,m,0,0") - (match_operand:DF 2 "vector_move_operand" " x,v,1,m,m,C,x,m")))] + (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,m,m,0,x,m,0,0") + (match_operand:DF 2 "vector_move_operand" " x,x,v,1,1,m,m,C,x,m")))] "TARGET_SSE && (!(MEM_P (operands[1]) && MEM_P (operands[2])) || (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))" "@ unpcklpd\t{%2, %0|%0, %2} vunpcklpd\t{%2, %1, %0|%0, %1, %2} + vunpcklpd\t{%2, %1, %0|%0, %1, %2} %vmovddup\t{%1, %0|%0, %1} + vmovddup\t{%1, %0|%0, %1} movhpd\t{%2, %0|%0, %2} vmovhpd\t{%2, %1, %0|%0, %1, %2} %vmovsd\t{%1, %0|%0, %1} movlhps\t{%2, %0|%0, %2} movhps\t{%2, %0|%0, %2}" - [(set_attr "isa" "sse2_noavx,avx,sse3,sse2_noavx,avx,sse2,noavx,noavx") + [(set_attr "isa" "sse2_noavx,avx,avx512vl,sse3,avx512vl,sse2_noavx,avx,sse2,noavx,noavx") (set (attr "type") (if_then_else (eq_attr "alternative" "0,1,2") (const_string "sselog") (const_string "ssemov"))) - (set_attr "prefix_data16" "*,*,*,1,*,*,*,*") - (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex,orig,orig") - (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,DF,V4SF,V2SF")]) + (set_attr "prefix_data16" "*,*,*,*,*,1,*,*,*,*") + (set_attr "prefix" "orig,vex,evex,maybe_vex,evex,orig,vex,maybe_vex,orig,orig") + (set_attr "mode" "V2DF,V2DF,V2DF, DF, DF, V1DF,V1DF,DF,V4SF,V2SF")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;