From patchwork Tue May 5 13:03:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Tocar X-Patchwork-Id: 468119 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D60E2140134 for ; Tue, 5 May 2015 23:03:50 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=CRLvMjq0; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=jf1wlNdDLH3Q0Z+mO MDLwVN5c2gNXgBvtQCCPRly3Fh1ypXZQ3o7P1GWEAaFCubVVgpnR9pFGyiu0RgJR GeBFAna80JBa1y1tsytudOPVnYxLKt6xYwRSKLt/ax/C5ult5YBIyJOeYhouDElk WvslUYDYngoF4C7Sax75KsQ2wY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=pbrvXiK6viHik8ypn1DMea6 2nQw=; b=CRLvMjq0VW3QiyOZL4DadqPyFsBHyK/VoG291Q9F8nvqTs75Ht8ErXv JLofXhuKq4+ZjZ0o5NtD6c9KgbUD9nkHC5Y2PKMj7oxbT+6+vlOeQYeynFmqAi+6 3Waf+1EjX+pGWkg9fqhEVxq5fS264NsKnY63UB3fKOO82sn4a6E8= Received: (qmail 62398 invoked by alias); 5 May 2015 13:03:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 62382 invoked by uid 89); 5 May 2015 13:03:41 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-yh0-f47.google.com Received: from mail-yh0-f47.google.com (HELO mail-yh0-f47.google.com) (209.85.213.47) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 05 May 2015 13:03:40 +0000 Received: by yhw29 with SMTP id 29so40069453yhw.1 for ; Tue, 05 May 2015 06:03:38 -0700 (PDT) X-Received: by 10.50.78.199 with SMTP id d7mr1625638igx.18.1430831018705; Tue, 05 May 2015 06:03:38 -0700 (PDT) Received: from msticlxl7.ims.intel.com (jfdmzpr05-ext.jf.intel.com. [134.134.139.74]) by mx.google.com with ESMTPSA id l3sm7238783ige.21.2015.05.05.06.03.35 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 May 2015 06:03:37 -0700 (PDT) Date: Tue, 5 May 2015 16:03:24 +0300 From: Ilya Tocar To: Uros Bizjak Cc: "H.J. Lu" , Kirill Yukhin , GCC Patches Subject: Re: [PATCH, PR65915] Fix float conversion split. Message-ID: <20150505130324.GA47477@msticlxl7.ims.intel.com> References: <20150319092404.GA73948@msticlxl7.ims.intel.com> <20150323160222.GB10265@msticlxl7.ims.intel.com> <20150324134311.GA40649@msticlxl57.ims.intel.com> <20150428162049.GA62528@msticlxl7.ims.intel.com> <20150430151512.GA106194@msticlxl7.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes > >> +++ b/gcc/testsuite/gcc.target/i386/pr65915.c > >> @@ -0,0 +1,6 @@ > >> +/* { dg-do run } */ > >> +/* { dg-options "-O2 -mavx512f -fpic -mcmodel=medium" } */ > >> +/* { dg-require-effective-target avx512f } */ > >> +/* { dg-require-effective-target lp64 } */ > >> + > >> +#include "avx512f-vrndscalepd-2.c" > > > > Missing testcases for > > > > FAIL: gcc.target/i386/avx512f-vrndscaleps-2.c (test for excess errors) > > FAIL: gcc.target/i386/avx512vl-vrndscaleps-2.c (internal compiler error) > > The attached test is OK, since these two would test for the same problem. > > > as well as ChangeLog entries. > > ChangeLog is missing. Please add PR number and describe *each* change > accurately. You can say (vector convert to float spltiter) for this > particular nameless splitter. > > Please repost the patch with updated ChangeLog. > ChangeLog PR c/65915 * config/i386/i386.md (vector convert to float spltiter): Check for xmm16+, when splitting scalar float conversion. * config/i386/sse.md (sse2_cvtsi2sd): Support EVEX version. And for tests PR c/65915 * gcc.target/i386/pr65915.c: New. Reposted patch below. --- gcc/config/i386/i386.md | 8 ++++++-- gcc/config/i386/sse.md | 6 +++--- gcc/testsuite/gcc.target/i386/pr65915.c | 6 ++++++ 3 files changed, 15 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr65915.c diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 937871a..af1cd9b 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -4897,7 +4897,9 @@ "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed && SSE_REG_P (operands[0]) - && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)" + && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC) + && (!EXT_REX_SSE_REG_P (operands[0]) + || TARGET_AVX512VL)" [(const_int 0)] { operands[3] = simplify_gen_subreg (mode, operands[0], @@ -4921,7 +4923,9 @@ "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_SSE_PARTIAL_REG_DEPENDENCY && optimize_function_for_speed_p (cfun) - && reload_completed && SSE_REG_P (operands[0])" + && reload_completed && SSE_REG_P (operands[0]) + && (!EXT_REX_SSE_REG_P (operands[0]) + || TARGET_AVX512VL)" [(const_int 0)] { const machine_mode vmode = mode; diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 9b7009a..c61098d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4258,11 +4258,11 @@ (set_attr "mode" "TI")]) (define_insn "sse2_cvtsi2sd" - [(set (match_operand:V2DF 0 "register_operand" "=x,x,x") + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v") (vec_merge:V2DF (vec_duplicate:V2DF (float:DF (match_operand:SI 2 "nonimmediate_operand" "r,m,rm"))) - (match_operand:V2DF 1 "register_operand" "0,0,x") + (match_operand:V2DF 1 "register_operand" "0,0,v") (const_int 1)))] "TARGET_SSE2" "@ @@ -4275,7 +4275,7 @@ (set_attr "amdfam10_decode" "vector,double,*") (set_attr "bdver1_decode" "double,direct,*") (set_attr "btver2_decode" "double,double,double") - (set_attr "prefix" "orig,orig,vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "DF")]) (define_insn "sse2_cvtsi2sdq" diff --git a/gcc/testsuite/gcc.target/i386/pr65915.c b/gcc/testsuite/gcc.target/i386/pr65915.c new file mode 100644 index 0000000..990c5aa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr65915.c @@ -0,0 +1,6 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f -fpic -mcmodel=medium" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-require-effective-target lp64 } */ + +#include "avx512f-vrndscalepd-2.c"