| Message ID | 20150114115649.GB66571@msticlxl7.ims.intel.com |
|---|---|
| State | New |
| Headers | show |
On Wed, Jan 14, 2015 at 12:56 PM, Ilya Tocar <tocarip.intel@gmail.com> wrote: > Hi, > > This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64393 > It makes -mavx512vbmi enable avx512bw, as it requires 64-bit masks. > OK for trunk? > > ChangeLog: > > gcc/ > PR target/64393 > * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI_SET): > Enable AVX512BW. > (OPTION_MASK_ISA_AVX512BW_UNSET): Disable AVX512BW. > * config/i386/i386.c (ix86_hard_regno_mode_ok): Don't check > AVX512VBMI, as it implies AVX512BW. > > testsuite/ > PR target/64393 > * gcc.target/i386/pr64393.c: New test. OK. Thanks, Uros.
On Wed, Jan 14, 2015 at 4:08 AM, Uros Bizjak <ubizjak@gmail.com> wrote: > On Wed, Jan 14, 2015 at 12:56 PM, Ilya Tocar <tocarip.intel@gmail.com> wrote: >> Hi, >> >> This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64393 >> It makes -mavx512vbmi enable avx512bw, as it requires 64-bit masks. >> OK for trunk? >> >> ChangeLog: >> >> gcc/ >> PR target/64393 >> * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI_SET): >> Enable AVX512BW. >> (OPTION_MASK_ISA_AVX512BW_UNSET): Disable AVX512BW. ^^^^^^^^^^^^^^^ Typo. >> * config/i386/i386.c (ix86_hard_regno_mode_ok): Don't check >> AVX512VBMI, as it implies AVX512BW. >> >> testsuite/ >> PR target/64393 >> * gcc.target/i386/pr64393.c: New test. > > OK. > > Thanks, > Uros.
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 77edb47..4e5687a 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -74,7 +74,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_AVX512IFMA_SET \ (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET) #define OPTION_MASK_ISA_AVX512VBMI_SET \ - (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512F_SET) + (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET) #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED @@ -171,7 +171,8 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ -#define OPTION_MASK_ISA_AVX512BW_UNSET OPTION_MASK_ISA_AVX512BW +#define OPTION_MASK_ISA_AVX512BW_UNSET \ + (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET) #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 7a39f80..91eae5a 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -41669,7 +41669,7 @@ ix86_hard_regno_mode_ok (int regno, machine_mode mode) return VALID_FP_MODE_P (mode); if (MASK_REGNO_P (regno)) return (VALID_MASK_REG_MODE (mode) - || ((TARGET_AVX512BW || TARGET_AVX512VBMI) + || (TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE (mode))); if (BND_REGNO_P (regno)) return VALID_BND_REG_MODE (mode); diff --git a/gcc/testsuite/gcc.target/i386/pr64393.c b/gcc/testsuite/gcc.target/i386/pr64393.c new file mode 100644 index 0000000..37a0e48 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr64393.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mavx512vbmi" } */ + +int a[1024]; + +void +foo (int i) +{ + for (;; i++) + if (a[i] != (i ^ (i * 3) ^ (i * 7))) + return; +}