From patchwork Sat Jan 10 13:30:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allan Sandfeld Jensen X-Patchwork-Id: 427351 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7D64714018C for ; Sun, 11 Jan 2015 00:30:55 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:cc:references:in-reply-to:mime-version :content-type:message-id; q=dns; s=default; b=qBmX3uHRTBu2LKrVYx TrbUjZha24aybLAPsIRz0ulSIelZrLYFyJrBa3hKS6mFWG4jPXeXJirllhXNfGjA IxVCINKFTLC7Dus/1r3V3R+uKyiRi77ozA22NAbSon50S6pdLNhuZL5dgnd2008G p+SUIHQAlyg6+88/USwBZq16M= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:cc:references:in-reply-to:mime-version :content-type:message-id; s=default; bh=m2IhBgq89loo9mdIZrBcJ0uS 2ek=; b=gPtJ0ZRf3+McVFNW4ppDy4K9+/nOOUS0cVNNlJajuH2T4Kt9fXYVk29L XSreVumvl8k1+jwCaHhWCpaXCh4jE0VICQW8gnW0cSu+LLBP6Jk54e7hXpDGvj16 UBP89XE986cNLd6NgyrWyy4NOJjRB96ekMIh+dzHSHTMzPOt4aQ= Received: (qmail 29032 invoked by alias); 10 Jan 2015 13:30:47 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 29021 invoked by uid 89); 10 Jan 2015 13:30:45 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f176.google.com Received: from mail-wi0-f176.google.com (HELO mail-wi0-f176.google.com) (209.85.212.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Sat, 10 Jan 2015 13:30:41 +0000 Received: by mail-wi0-f176.google.com with SMTP id ex7so7106192wid.3 for ; Sat, 10 Jan 2015 05:30:38 -0800 (PST) X-Received: by 10.180.73.170 with SMTP id m10mr14327551wiv.72.1420896638570; Sat, 10 Jan 2015 05:30:38 -0800 (PST) Received: from princessluna.localnet (p57A055B3.dip0.t-ipconnect.de. [87.160.85.179]) by mx.google.com with ESMTPSA id a14sm2337147wib.22.2015.01.10.05.30.37 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 10 Jan 2015 05:30:37 -0800 (PST) From: Allan Sandfeld Jensen To: gcc-patches@gcc.gnu.org, Jakub Jelinek Subject: Re: [Patch, i386] Support BMI and BMI2 targets in multiversioning Date: Sat, 10 Jan 2015 14:30:35 +0100 User-Agent: KMail/1.13.7 (Linux/3.16.0-4-amd64; KDE/4.14.1; x86_64; ; ) Cc: "H.J. Lu" References: <201412311328.48412.linux@carewolf.com> <20141231131542.GV1667@tucnak.redhat.com> In-Reply-To: <20141231131542.GV1667@tucnak.redhat.com> MIME-Version: 1.0 Message-Id: <201501101430.36007.linux@carewolf.com> X-IsSubscribed: yes On Wednesday 31 December 2014, Jakub Jelinek wrote: > On Wed, Dec 31, 2014 at 01:28:47PM +0100, Allan Sandfeld Jensen wrote: > > I recently wanted to use multiversioning for BMI2 specific extensions > > PDEP/PEXT, and noticed it wasn't there. So I wrote this patch to add it, > > and also added AES, F16C and BMI1 for completeness. > > AES nor F16C doesn't make any sense IMHO for multiversioning, you need > special intrinsics for that anyway and when you use them, the function will > fail to compile without those features. > Multiversioning only makes sense for ISA features the compiler uses for > normal C/C++ code without any intrinsics. > Patch reduced to just adding BMI and BMI2 multiversioning: Best regards `Allan commit aa5b98407bcc3ae2f1fef70455b89447112c3e2c Author: Allan Sandfeld Jensen Date: Fri Dec 26 21:14:01 2014 +0100 BMI and BMI2 multiversion support diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ff8a5e6..6afd58a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2014-12-29 Allan Sandfeld Jensen + + * config/i386/i386.c (get_builtin_code_for_version): Add + support for BMI and BMI2 multiversion functions. + 2014-12-27 H.J. Lu PR target/64409 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index d693fdb..9ae9bca 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -34261,15 +34261,18 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) P_PROC_SSE4_A, P_SSE4_1, P_SSE4_2, - P_PROC_SSE4_2, P_POPCNT, + P_PROC_SSE4_2, P_AVX, P_PROC_AVX, + P_BMI, + P_PROC_BMI, P_FMA4, P_XOP, P_PROC_XOP, P_FMA, P_PROC_FMA, + P_BMI2, P_AVX2, P_PROC_AVX2, P_AVX512F, @@ -34295,12 +34298,14 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) {"sse4a", P_SSE4_A}, {"ssse3", P_SSSE3}, {"sse4.1", P_SSE4_1}, - {"sse4.2", P_SSE4_2}, {"popcnt", P_POPCNT}, + {"sse4.2", P_SSE4_2}, {"avx", P_AVX}, + {"bmi", P_BMI}, {"fma4", P_FMA4}, {"xop", P_XOP}, {"fma", P_FMA}, + {"bmi2", P_BMI2}, {"avx2", P_AVX2}, {"avx512f", P_AVX512F} }; @@ -34395,7 +34400,7 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) break; case PROCESSOR_BTVER2: arg_str = "btver2"; - priority = P_PROC_AVX; + priority = P_PROC_BMI; break; case PROCESSOR_BDVER1: arg_str = "bdver1"; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ef6ddcc..5b11622 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2014-12-29 Allan Sandfeld Jensen + + * gcc.target/i386/funcspec-5.c: Test new multiversion targets. + * g++.dg/ext/mv17.C: Test BMI/BMI2 multiversion dispatcher. + 2014-12-28 H.J. Lu * gcc.target/i386/pr57003.c: Skip on x32. diff --git a/gcc/testsuite/g++.dg/ext/mv17.C b/gcc/testsuite/g++.dg/ext/mv17.C new file mode 100644 index 0000000..311f217 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/mv17.C @@ -0,0 +1,91 @@ +/* Test case to check if Multiversioning works for BMI and BMI2. */ +/* { dg-do run { target i?86-*-* x86_64-*-* } } */ +/* { dg-options "-O2" } */ + +#include + +// Check BMI feature selection works +int foo () __attribute__((target("default"))); +int foo () __attribute__((target("bmi"))); +int foo () __attribute__((target("bmi2"))); + +// Check specialized versions for archs with BMI is chosen over generic BMI versions. +int bar () __attribute__((target("default"))); +int bar () __attribute__((target("bmi"))); +int bar () __attribute__((target("bmi2"))); +int bar () __attribute__((target("arch=btver2"))); +int bar () __attribute__((target("arch=haswell"))); + +int main () +{ + int val = foo (); + + if (__builtin_cpu_supports ("bmi2")) + assert (val == 2); + else if (__builtin_cpu_supports ("bmi")) + assert (val == 1); + else + assert (val == 0); + + val = bar (); + + if (__builtin_cpu_is ("btver2") + assert (val == 5); + else if (__builtin_cpu_is ("haswell")) + assert (val == 6); + else if (__builtin_cpu_supports ("bmi2")) + assert (val == 2); + else if (__builtin_cpu_supports ("bmi")) + assert (val == 1); + else + assert (val == 0); + + return 0; +} + +int __attribute__ ((target("default"))) +foo () +{ + return 0; +} + +int __attribute__ ((target("bmi"))) +foo () +{ + return 1; +} +int __attribute__ ((target("bmi2"))) +foo () +{ + return 2; +} + +int __attribute__ ((target("default"))) +bar () +{ + return 0; +} + +int __attribute__ ((target("bmi"))) +bar () +{ + return 1; +} +int __attribute__ ((target("bmi2"))) +bar () +{ + return 2; +} + +int __attribute__ ((target("arch=btver2"))) +bar () +{ + return 5; +} + +int __attribute__ ((target("arch=haswell"))) +bar () +{ + return 6; +} + diff --git a/gcc/testsuite/gcc.target/i386/funcspec-5.c b/gcc/testsuite/gcc.target/i386/funcspec-5.c index 269e610..2e316a7 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-5.c +++ b/gcc/testsuite/gcc.target/i386/funcspec-5.c @@ -25,6 +25,8 @@ extern void test_tbm (void) __attribute__((__target__("tbm"))); extern void test_avx (void) __attribute__((__target__("avx"))); extern void test_avx2 (void) __attribute__((__target__("avx2"))); extern void test_avx512 (void) __attribute__((__target__("avx512"))); +extern void test_bmi (void) __attribute__((__target__("bmi"))); +extern void test_bmi2 (void) __attribute__((__target__("bmi2"))); extern void test_no_abm (void) __attribute__((__target__("no-abm"))); extern void test_no_aes (void) __attribute__((__target__("no-aes"))); @@ -48,6 +50,8 @@ extern void test_no_tbm (void) __attribute__((__target__("no-tbm"))); extern void test_no_avx (void) __attribute__((__target__("no-avx"))); extern void test_no_avx2 (void) __attribute__((__target__("no-avx2"))); extern void test_no_avx512 (void) __attribute__((__target__("no-avx512"))); +extern void test_no_bmi (void) __attribute__((__target__("no-bmi"))); +extern void test_no_bmi2 (void) __attribute__((__target__("no-bmi2"))); extern void test_arch_i386 (void) __attribute__((__target__("arch=i386"))); extern void test_arch_i486 (void) __attribute__((__target__("arch=i486"))); diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index efd08c4..0b2beee 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,9 @@ +2014-12-29 Allan Sandfeld Jensen + + * config/i386/cpuinfo.c (enum processor_features): Add FEATURE_BMI and + FEATURE_BMI2. + (get_available_features): Detect FEATURE_BMI and FEATURE_BMI2. + 2014-12-19 Matthew Fortune * config.host: Support mipsisa32r6 and mipsisa64r6. diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c index 8ca385c..3c22f2d 100644 --- a/libgcc/config/i386/cpuinfo.c +++ b/libgcc/config/i386/cpuinfo.c @@ -97,7 +97,9 @@ enum processor_features FEATURE_FMA4, FEATURE_XOP, FEATURE_FMA, - FEATURE_AVX512F + FEATURE_AVX512F, + FEATURE_BMI, + FEATURE_BMI2 }; struct __processor_model @@ -277,8 +279,12 @@ get_available_features (unsigned int ecx, unsigned int edx, { unsigned int eax, ebx, ecx, edx; __cpuid_count (7, 0, eax, ebx, ecx, edx); + if (ebx & bit_BMI) + features |= (1 << FEATURE_BMI); if (ebx & bit_AVX2) features |= (1 << FEATURE_AVX2); + if (ebx & bit_BMI2) + features |= (1 << FEATURE_BMI2); if (ebx & bit_AVX512F) features |= (1 << FEATURE_AVX512F); }