From patchwork Wed Dec 10 14:00:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 419664 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 81182140082 for ; Thu, 11 Dec 2014 01:00:48 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=LC1IBbGIs3aME5lJO wUVnyb7u25IlUq3hMz8uXbFdVt5PDRgPb14F3Sv6HK5FtI3EyH9bg33rBaVpRNUz m40vqwsteMMASZR3SBlI/ML3uns2tEMPqUPPJoSNnJcrN/bNFjCeOkgSVYlqxZv9 NkmbVIYHZRmkpjsOOSRkZulZ1E= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=LLX1oaBLyzkVuwaGEO4V5zA vwbE=; b=UC/LQAUtmz02D3lrP6Lhtj1IO4UplyzBxdJ84Ix/wcMXuN3d5wY+DSj c8vSWc8r+JcF29EB8X0qRBk+1d814lgv8w3OwH4DS/fMRvmxjKVNUwaCYN/V+0qV bDdoEU8dZqUuHymucxdEkd1clkmhJRwe7oWS/W09N0l1TSCnmEVA= Received: (qmail 14225 invoked by alias); 10 Dec 2014 14:00:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 14209 invoked by uid 89); 10 Dec 2014 14:00:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, SPF_HELO_PASS, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gate.crashing.org Received: from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Wed, 10 Dec 2014 14:00:36 +0000 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id sBAE0UeN016215; Wed, 10 Dec 2014 08:00:31 -0600 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id sBAE0UoD016214; Wed, 10 Dec 2014 08:00:30 -0600 Date: Wed, 10 Dec 2014 08:00:30 -0600 From: Segher Boessenkool To: David Edelsohn Cc: GCC Patches Subject: Re: [PATCH 06/10] rs6000: New add/subf carry insns Message-ID: <20141210140030.GA15905@gate.crashing.org> References: <72cecd52901018524525d156113b1be658917f6b.1418024189.git.segher@kernel.crashing.org> Mime-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.3i X-IsSubscribed: yes On Mon, Dec 08, 2014 at 10:53:21AM -0500, David Edelsohn wrote: > As we both noticed, there are a few problems with this patch, so I'll > wait for a revised version. Here it is. It took a bit longer because of a latent problem in combine (ugh!) that caused mysterious failures in guality (double ugh). For the carry_in patterns I now have an expander that expands to the _0 and _m1 cases directly. Okay for mainline? Cheers, Segher 2014-12-10 Segher Boessenkool gcc/ PR target/64180 * config/rs6000/predicates.md (adde_operand): New. * config/rs6000/rs6000.md (add3_carry): New. (*add3_imm_carry_pos): New. (*add3_imm_carry_0): New. (*add3_imm_carry_m1): New. (*add3_imm_carry_neg): New. (add3_carry_in): New. (*add3_carry_in): New. (add3_carry_in_0): New. (add3_carry_in_m1): New. (subf3_carry): New. (*subf3_imm_carry_0): New. (*subf3_imm_carry_m1): New. (subf3_carry_in): New. (*subf3_carry_in): New. (subf3_carry_in_0): New. (subf3_carry_in_m1): New. (subf3_carry_in_xx): New. --- gcc/config/rs6000/predicates.md | 6 ++ gcc/config/rs6000/rs6000.md | 200 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 206 insertions(+) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index ea230a5..a19cb2f 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -788,6 +788,12 @@ (define_predicate "add_operand" || satisfies_constraint_L (op)") (match_operand 0 "gpc_reg_operand"))) +;; Return 1 if the operand is either a non-special register, or 0, or -1. +(define_predicate "adde_operand" + (if_then_else (match_code "const_int") + (match_test "INTVAL (op) == 0 || INTVAL (op) == -1") + (match_operand 0 "gpc_reg_operand"))) + ;; Return 1 if OP is a constant but not a valid add_operand. (define_predicate "non_add_cint_operand" (and (match_code "const_int") diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index dcdb7c1..63ca3c2 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1634,6 +1634,115 @@ (define_split FAIL; }) + +(define_insn "add3_carry" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (plus:P (match_operand:P 1 "gpc_reg_operand" "r") + (match_operand:P 2 "reg_or_short_operand" "rI"))) + (set (reg:P CA_REGNO) + (ltu:P (plus:P (match_dup 1) + (match_dup 2)) + (match_dup 1)))] + "" + "add%I2c %0,%1,%2" + [(set_attr "type" "add")]) + +(define_insn "*add3_imm_carry_pos" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (plus:P (match_operand:P 1 "gpc_reg_operand" "r") + (match_operand:P 2 "short_cint_operand" "n"))) + (set (reg:P CA_REGNO) + (geu:P (match_dup 1) + (match_operand:P 3 "const_int_operand" "n")))] + "INTVAL (operands[2]) > 0 + && INTVAL (operands[2]) + INTVAL (operands[3]) == 0" + "addic %0,%1,%2" + [(set_attr "type" "add")]) + +(define_insn "*add3_imm_carry_0" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (match_operand:P 1 "gpc_reg_operand" "r")) + (set (reg:P CA_REGNO) + (const_int 0))] + "" + "addic %0,%1,0" + [(set_attr "type" "add")]) + +(define_insn "*add3_imm_carry_m1" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (plus:P (match_operand:P 1 "gpc_reg_operand" "r") + (const_int -1))) + (set (reg:P CA_REGNO) + (ne:P (match_dup 1) + (const_int 0)))] + "" + "addic %0,%1,-1" + [(set_attr "type" "add")]) + +(define_insn "*add3_imm_carry_neg" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (plus:P (match_operand:P 1 "gpc_reg_operand" "r") + (match_operand:P 2 "short_cint_operand" "n"))) + (set (reg:P CA_REGNO) + (gtu:P (match_dup 1) + (match_operand:P 3 "const_int_operand" "n")))] + "INTVAL (operands[2]) < 0 + && INTVAL (operands[2]) + INTVAL (operands[3]) == -1" + "addic %0,%1,%2" + [(set_attr "type" "add")]) + + +(define_expand "add3_carry_in" + [(parallel [ + (set (match_operand:GPR 0 "gpc_reg_operand") + (plus:GPR (plus:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "adde_operand")) + (reg:GPR CA_REGNO))) + (clobber (reg:GPR CA_REGNO))])] + "" +{ + if (operands[2] == const0_rtx) + { + emit_insn (gen_add3_carry_in_0 (operands[0], operands[1])); + DONE; + } + if (operands[2] == constm1_rtx) + { + emit_insn (gen_add3_carry_in_m1 (operands[0], operands[1])); + DONE; + } +}) + +(define_insn "*add3_carry_in" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (plus:GPR (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "gpc_reg_operand" "r")) + (reg:GPR CA_REGNO))) + (clobber (reg:GPR CA_REGNO))] + "" + "adde %0,%1,%2" + [(set_attr "type" "add")]) + +(define_insn "add3_carry_in_0" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (reg:GPR CA_REGNO))) + (clobber (reg:GPR CA_REGNO))] + "" + "addze %0,%1" + [(set_attr "type" "add")]) + +(define_insn "add3_carry_in_m1" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (plus:GPR (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (reg:GPR CA_REGNO)) + (const_int -1))) + (clobber (reg:GPR CA_REGNO))] + "" + "addme %0,%1" + [(set_attr "type" "add")]) + + (define_expand "one_cmpl2" [(set (match_operand:SDI 0 "gpc_reg_operand" "") (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))] @@ -1772,6 +1881,97 @@ (define_insn "subf3_imm" [(set_attr "type" "add")]) +(define_insn "subf3_carry" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (minus:P (match_operand:P 2 "reg_or_short_operand" "rI") + (match_operand:P 1 "gpc_reg_operand" "r"))) + (set (reg:P CA_REGNO) + (leu:P (match_dup 1) + (match_dup 2)))] + "" + "subf%I2c %0,%1,%2" + [(set_attr "type" "add")]) + +(define_insn "*subf3_imm_carry_0" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (neg:P (match_operand:P 1 "gpc_reg_operand" "r"))) + (set (reg:P CA_REGNO) + (eq:P (match_dup 1) + (const_int 0)))] + "" + "subfic %0,%1,0" + [(set_attr "type" "add")]) + +(define_insn "*subf3_imm_carry_m1" + [(set (match_operand:P 0 "gpc_reg_operand" "=r") + (not:P (match_operand:P 1 "gpc_reg_operand" "r"))) + (set (reg:P CA_REGNO) + (const_int 1))] + "" + "subfic %0,%1,-1" + [(set_attr "type" "add")]) + + +(define_expand "subf3_carry_in" + [(parallel [ + (set (match_operand:GPR 0 "gpc_reg_operand") + (plus:GPR (plus:GPR (not:GPR (match_operand:GPR 1 "gpc_reg_operand")) + (reg:GPR CA_REGNO)) + (match_operand:GPR 2 "adde_operand"))) + (clobber (reg:GPR CA_REGNO))])] + "" +{ + if (operands[2] == const0_rtx) + { + emit_insn (gen_subf3_carry_in_0 (operands[0], operands[1])); + DONE; + } + if (operands[2] == constm1_rtx) + { + emit_insn (gen_subf3_carry_in_m1 (operands[0], operands[1])); + DONE; + } +}) + +(define_insn "*subf3_carry_in" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (plus:GPR (plus:GPR (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")) + (reg:GPR CA_REGNO)) + (match_operand:GPR 2 "gpc_reg_operand" "r"))) + (clobber (reg:GPR CA_REGNO))] + "" + "subfe %0,%1,%2" + [(set_attr "type" "add")]) + +(define_insn "subf3_carry_in_0" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (plus:GPR (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")) + (reg:GPR CA_REGNO))) + (clobber (reg:GPR CA_REGNO))] + "" + "subfze %0,%1" + [(set_attr "type" "add")]) + +(define_insn "subf3_carry_in_m1" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (plus:GPR (minus:GPR (reg:GPR CA_REGNO) + (match_operand:GPR 1 "gpc_reg_operand" "r")) + (const_int -2))) + (clobber (reg:GPR CA_REGNO))] + "" + "subfme %0,%1" + [(set_attr "type" "add")]) + +(define_insn "subf3_carry_in_xx" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (plus:GPR (reg:GPR CA_REGNO) + (const_int -1))) + (clobber (reg:GPR CA_REGNO))] + "" + "subfe %0,%0,%0" + [(set_attr "type" "add")]) + + (define_expand "neg2" [(set (match_operand:SDI 0 "gpc_reg_operand" "") (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]