From patchwork Fri Dec 5 22:46:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 418314 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CE85A14010B for ; Sat, 6 Dec 2014 09:46:35 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; q=dns; s= default; b=GzvRUfK5Nz5NIfwHoFlohJxP/+Yq+pFcaf3a5LIAfd+Ic05PPPWCT GijyJp1E0dXB6L+OpLRqKheG3ubJ3spdM2oOtuxZEqj/xJX0KZPwEHA0fp6ZpRux hgACfWM1Cc7uDwevU/hZFY+RRZLuU2Xd1qMDXZyOWVZ2kjLEfKGLtw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; s= default; bh=MaBbR/2eZ8oXJXTR8zWInH1s+xQ=; b=TUFg45qpLGXuKAaOB6eB X8zMYMKZNnztccl5GCW/2o8O3yry8Kke5EBFGyOrPX2ZmPV+BBfoaP+FdDqVW4Ft aDMISSNr5tJnsUBbVxs+MtXWLcbjIGiUodAyV5NDacIbOWvgJsKQFl85gaLF+tiz Iwe30h2lXCuXyn+AHjrKMhA= Received: (qmail 4794 invoked by alias); 5 Dec 2014 22:46:17 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 4670 invoked by uid 89); 5 Dec 2014 22:46:16 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL, BAYES_00 autolearn=ham version=3.3.2 X-HELO: e35.co.us.ibm.com Received: from e35.co.us.ibm.com (HELO e35.co.us.ibm.com) (32.97.110.153) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Fri, 05 Dec 2014 22:46:15 +0000 Received: from /spool/local by e35.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 5 Dec 2014 15:46:12 -0700 Received: from b03cxnp08027.gho.boulder.ibm.com (b03cxnp08027.gho.boulder.ibm.com [9.17.130.19]) by d03dlp02.boulder.ibm.com (Postfix) with ESMTP id C87E43E4003F for ; Fri, 5 Dec 2014 15:46:11 -0700 (MST) Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id sB5MkBOF17760276 for ; Fri, 5 Dec 2014 15:46:11 -0700 Received: from d03av02.boulder.ibm.com (localhost [127.0.0.1]) by d03av02.boulder.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id sB5MkBfG020891 for ; Fri, 5 Dec 2014 15:46:11 -0700 Received: from ibm-tiger.the-meissners.org (dhcp-9-32-77-206.usma.ibm.com [9.32.77.206]) by d03av02.boulder.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id sB5MkBFN020836; Fri, 5 Dec 2014 15:46:11 -0700 Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 102534219F; Fri, 5 Dec 2014 17:46:09 -0500 (EST) Date: Fri, 5 Dec 2014 17:46:09 -0500 From: Michael Meissner To: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com Subject: [PATCH], PR 64204, Fix long double constants on powerpc little endian Message-ID: <20141205224609.GA14320@ibm-tiger.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14120522-0013-0000-0000-000006CED45E X-IsSubscribed: yes After my upper regs patches went in, I noticed that the gcc.dg/c11-atomic-2.c test would fail on a power8 host that was running in little endian mode. This particular test only fails if you are compiling this code with no optimization, and power8 selected as the cpu. Ultimately, it fails in reload when an array index is way out of bounds. In looking at it, it is due to rs6000_emit_move creating two separate moves of SUBREG's of TFmode to assign a constant during RTL generation. I fixed this so this 'optimization' is only done if DFmode values can only go in the traditional registers. While I was at it, I optimized setting TFmode variables to 0.0L to use xxlxor rather than loading up 2 double words of memory. I have done bootstraps on big endian power7, big endian power8, and little endian power8 with no regressions in the test suite. I also have built the Spec 2006 test suite for power7. Can I install these patches? 2014-12-05 Michael Meissner PR target/64204 * config/rs6000/rs6000.c (rs6000_emit_move): Do not split TFmode constant moves if -mupper-regs-df. * config/rs6000/rs6000.md (mov_64bit_dm): Optimize moving 0.0L to TFmode. (movtd_64bit_nodm): Likewise. (mov_32bit, FMOVE128 case): Likewise. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 218388) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -8396,9 +8396,11 @@ rs6000_emit_move (rtx dest, rtx source, || ! nonimmediate_operand (operands[0], mode))) goto emit_set; - /* 128-bit constant floating-point values on Darwin should really be - loaded as two parts. */ + /* 128-bit constant floating-point values on Darwin should really be loaded + as two parts. However, this premature splitting is a problem when DFmode + values can go into Altivec registers. */ if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 + && !reg_addr[DFmode].scalar_in_vmx_p && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE) { rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0), Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 218388) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -8086,8 +8086,8 @@ (define_expand "mov" ;; problematical. Don't allow direct move for this case. (define_insn_and_split "*mov_64bit_dm" - [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm") - (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))] + [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r,r,wm") + (match_operand:FMOVE128 1 "input_operand" "d,m,d,j,r,jYGHF,r,wm,r"))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && (mode != TDmode || WORDS_BIG_ENDIAN) && (gpc_reg_operand (operands[0], mode) @@ -8096,11 +8096,11 @@ (define_insn_and_split "*mov_64bit "&& reload_completed" [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "length" "8,8,8,12,12,8,8,8")]) + [(set_attr "length" "8,8,8,8,12,12,8,8,8")]) (define_insn_and_split "*movtd_64bit_nodm" - [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r") - (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))] + [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r") + (match_operand:TD 1 "input_operand" "d,m,d,j,r,jYGHF,r"))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN && (gpc_reg_operand (operands[0], TDmode) || gpc_reg_operand (operands[1], TDmode))" @@ -8108,11 +8108,11 @@ (define_insn_and_split "*movtd_64bit_nod "&& reload_completed" [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "length" "8,8,8,12,12,8")]) + [(set_attr "length" "8,8,8,8,12,12,8")]) (define_insn_and_split "*mov_32bit" - [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r") - (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))] + [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r") + (match_operand:FMOVE128 1 "input_operand" "d,m,d,j,r,jYGHF,r"))] "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64 && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -8120,7 +8120,7 @@ (define_insn_and_split "*mov_32bit "&& reload_completed" [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "length" "8,8,8,20,20,16")]) + [(set_attr "length" "8,8,8,8,20,20,16")]) (define_insn_and_split "*mov_softfloat" [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")