From patchwork Thu Oct 9 10:28:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 397983 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 83666140078 for ; Thu, 9 Oct 2014 21:29:06 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=MitkDkbQW3LW42DGvMzk6a8q9r1nUZWVpEHFt+aECpgMpJf1go bHbyf+QF9FjQIkIR9YTAbINR45cNu6nAIYnUxM9mM6bbq+Id9JVqc2cSf/h8437w 1f7Ogdi55ZkGszvZPXfDDsExvu8l93Sa6TeZhI8tNmrAaUEQG387Vu4VE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=mOw0rY3Y5doOQbpV1WH/QkJw+WI=; b=o9kMnnPhndYaJUhjAnke ifKhttaeaCFHEMIm9t2dI5RmmFceKJTJDb5CgOZoLYiklOxoAdnKtDHM9R04/kUz S7BjM9IhssGtGuPQ09kR9xAfeS09LrWotmAX6FSOxX3lA9pk8qATiD9iJqp1K4jn Kgj5j4kUv1O6KEQVIZJx1xM= Received: (qmail 27762 invoked by alias); 9 Oct 2014 10:28:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 27751 invoked by uid 89); 9 Oct 2014 10:28:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f176.google.com Received: from mail-wi0-f176.google.com (HELO mail-wi0-f176.google.com) (209.85.212.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Thu, 09 Oct 2014 10:28:57 +0000 Received: by mail-wi0-f176.google.com with SMTP id hi2so12675406wib.3 for ; Thu, 09 Oct 2014 03:28:54 -0700 (PDT) X-Received: by 10.180.107.100 with SMTP id hb4mr3010603wib.59.1412850534092; Thu, 09 Oct 2014 03:28:54 -0700 (PDT) Received: from msticlxl57.ims.intel.com (fmdmzpr01-ext.fm.intel.com. [192.55.54.36]) by mx.google.com with ESMTPSA id cu9sm3090149wjc.3.2014.10.09.03.28.50 for (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Oct 2014 03:28:53 -0700 (PDT) Date: Thu, 9 Oct 2014 14:28:41 +0400 From: Kirill Yukhin To: Uros Bizjak Cc: Jakub Jelinek , Richard Henderson , GCC Patches , kirill.yukhin@gmail.com Subject: [PATCH i386 AVX512] [66/n] Extend vpalignr insn patterns. Message-ID: <20141009102840.GB25028@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Hello, This patch extends vpalignr insn patterns. It also introduces dedicated `masked' version of pattern w/o substing. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/sse.md (define_mode_iterator SSESCALARMODE): Add V4TI mode. (define_insn "_palignr_mask"): New. (define_insn "_palignr"): Add EVEX version. --- Thanks, K diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a3b2477..79b6012 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -351,7 +351,7 @@ ;; ??? This should probably be dropped in favor of VIMAX_AVX2. (define_mode_iterator SSESCALARMODE - [(V2TI "TARGET_AVX2") TI]) + [(V4TI "TARGET_AVX512BW") (V2TI "TARGET_AVX2") TI]) (define_mode_iterator VI12_AVX2 [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI @@ -13621,11 +13621,33 @@ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) (set_attr "mode" "DI")]) +(define_insn "_palignr_mask" + [(set (match_operand:VI1_AVX2 0 "register_operand" "=v") + (vec_merge:VI1_AVX2 + (unspec:VI1_AVX2 + [(match_operand:VI1_AVX2 1 "register_operand" "v") + (match_operand:VI1_AVX2 2 "nonimmediate_operand" "vm") + (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")] + UNSPEC_PALIGNR) + (match_operand:VI1_AVX2 4 "vector_move_operand" "0C") + (match_operand: 5 "register_operand" "Yk")))] + "TARGET_AVX512BW && ( == 64 || TARGET_AVX512VL)" +{ + operands[3] = GEN_INT (INTVAL (operands[3]) / 8); + return "vpalignr\t{%3, %2, %1, %0%{%5%}%N4|%0%{%5%}%N4, %1, %2, %3}"; +} + [(set_attr "type" "sseishft") + (set_attr "atom_unit" "sishuf") + (set_attr "prefix_extra" "1") + (set_attr "length_immediate" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "_palignr" - [(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,x") + [(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,v") (unspec:SSESCALARMODE - [(match_operand:SSESCALARMODE 1 "register_operand" "0,x") - (match_operand:SSESCALARMODE 2 "nonimmediate_operand" "xm,xm") + [(match_operand:SSESCALARMODE 1 "register_operand" "0,v") + (match_operand:SSESCALARMODE 2 "nonimmediate_operand" "xm,vm") (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")] UNSPEC_PALIGNR))] "TARGET_SSSE3"