From patchwork Mon Sep 15 14:43:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Tocar X-Patchwork-Id: 389382 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B952214013A for ; Tue, 16 Sep 2014 00:43:47 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=OMKUtH1YUuzeVtrGU K2wZWQpieiK1P2Ky9k6HoIpulhN7MZvSew9I2ZOoKsv5w9miwqwJ5i17gb7kDd6r Z9GRLDYSOpA+TeoFTYa9T4ReB2nPvYDTSv7iMT4XTSnhApnmvnqhm8u69rldqGyk /B5bxoXUDJgoa0eNxedtJ2eYt0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=2LjSoEY1aZ3af8k3KwbouhB I4sE=; b=IXS4Zvw6L23PaMhkeqTScTNkuXFqBGZwnTd5FlJDmJR8jPWdFGJujQW W39KqF1/iPxcFpzRd4VYL4I4F1ywWbbKpg5YevpTLivP3JDaj32YoZTASy3XRjks e8tdBkBhNvy9od3itjaCJtYlRECuEOhgmIy2nHb2PXUL9NcqUY04= Received: (qmail 6413 invoked by alias); 15 Sep 2014 14:43:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 6401 invoked by uid 89); 15 Sep 2014 14:43:41 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-yk0-f172.google.com Received: from mail-yk0-f172.google.com (HELO mail-yk0-f172.google.com) (209.85.160.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 15 Sep 2014 14:43:39 +0000 Received: by mail-yk0-f172.google.com with SMTP id q9so2134627ykb.31 for ; Mon, 15 Sep 2014 07:43:37 -0700 (PDT) X-Received: by 10.236.202.70 with SMTP id c46mr35170159yho.0.1410792217725; Mon, 15 Sep 2014 07:43:37 -0700 (PDT) Received: from msticlxl7.ims.intel.com (jfdmzpr05-ext.jf.intel.com. [134.134.139.74]) by mx.google.com with ESMTPSA id c72sm5298034yhb.41.2014.09.15.07.43.35 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Sep 2014 07:43:37 -0700 (PDT) Date: Mon, 15 Sep 2014 18:43:27 +0400 From: Ilya Tocar To: Jakub Jelinek Cc: GCC Patches Subject: Re: [PATCH] PR62120 Message-ID: <20140915144327.GB1778@msticlxl7.ims.intel.com> References: <20140901104314.GB26266@msticlxl7.ims.intel.com> <20140901105552.GN17454@tucnak.redhat.com> <20140901143816.GC26266@msticlxl7.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20140901143816.GC26266@msticlxl7.ims.intel.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes On 01 Sep 18:38, Ilya Tocar wrote: > > Please mention the PR in the ChangeLog entry and add some testcases > > (can be gcc.target/i386/, but we should have it tested). > > Does this change anything on say register short sil __asm ("sil"); in 32-bit > > mode (when it IMHO should be rejected too?)? > > > Do we support "sil" at all? In i386.h i see: > > /* Note we are omitting these since currently I don't know how > to get gcc to use these, since they want the same but different > number as al, and ax. > */ > #define QI_REGISTER_NAMES \ > {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} > > And gcc doesn't recognize sil. > > Added testcase, and fixed avx512f-additional-reg-names.c to be valid on > 32 bits. Ok for trunk? > Slightly updated tests. Ok for trunk? gcc/ 2014-09-15 Ilya Tocar PR middle-end/62120 * varasm.c (decode_reg_name_and_count): Check availability for registers from ADDITIONAL_REGISTER_NAMES. Testsuite/ 2014-09-15 Ilya Tocar PR middle-end/62120 * gcc.target/i386/avx512f-additional-reg-names.c: Use register vaild in 32-bit mode. * gcc.target/i386/pr62120.c: New. --- gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c | 2 +- gcc/testsuite/gcc.target/i386/pr62120.c | 8 ++++++++ gcc/varasm.c | 5 +++-- 3 files changed, 12 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr62120.c diff --git a/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c b/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c index 164a1de..98a9052 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c @@ -3,7 +3,7 @@ void foo () { - register int zmm_var asm ("zmm9") __attribute__((unused)); + register int zmm_var asm ("zmm7") __attribute__((unused)); __asm__ __volatile__("vxorpd %%zmm0, %%zmm0, %%zmm7\n" : : : "zmm7" ); } diff --git a/gcc/testsuite/gcc.target/i386/pr62120.c b/gcc/testsuite/gcc.target/i386/pr62120.c new file mode 100644 index 0000000..bfb8c47 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr62120.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-sse" } */ + +void foo () +{ + register int zmm_var asm ("ymm9");/* { dg-error "invalid register name" } */ + register int zmm_var2 asm ("23");/* { dg-error "invalid register name" } */ +} diff --git a/gcc/varasm.c b/gcc/varasm.c index cd4a230..9c12b81 100644 --- a/gcc/varasm.c +++ b/gcc/varasm.c @@ -888,7 +888,7 @@ decode_reg_name_and_count (const char *asmspec, int *pnregs) if (asmspec[0] != 0 && i < 0) { i = atoi (asmspec); - if (i < FIRST_PSEUDO_REGISTER && i >= 0) + if (i < FIRST_PSEUDO_REGISTER && i >= 0 && reg_names[i][0]) return i; else return -2; @@ -925,7 +925,8 @@ decode_reg_name_and_count (const char *asmspec, int *pnregs) for (i = 0; i < (int) ARRAY_SIZE (table); i++) if (table[i].name[0] - && ! strcmp (asmspec, table[i].name)) + && ! strcmp (asmspec, table[i].name) + && reg_names[table[i].number][0]) return table[i].number; } #endif /* ADDITIONAL_REGISTER_NAMES */