From patchwork Thu Sep 11 13:16:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 388227 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1DABA14010C for ; Thu, 11 Sep 2014 23:17:08 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=atPYn0gz6HnejzbemDOB+A78lLAzPB6ato8pD92nyhhNlqe1qp E8qWLpsmOyQy8j0XHmMVQXTieFQx+kLzdxRN6TxewCjxBjqU9ryOkWvf86TDso2q VpJAfgKsvzwbAIQunFqIe77OqsjgSARJHBmGGubtwTOka/HtF8WckLW7w= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=p2C77p61SHJKT0iPKxsj7+RKWbY=; b=j6DtxNyOo8TJIq2h7187 UKoJpnmMc6DY4TxSGyQWzSMbGLRT70Qwv3OJvYNpAGYMAzKEEg17m/3hHKeafTww xNC5/ygizgtvbxHXBm2HyQy6YUzlPFkXgnS6VTz9dcZmRPUB7atTBdFE9DSKWOWw PwNPodSup+W/zngkuIvIAtM= Received: (qmail 18547 invoked by alias); 11 Sep 2014 13:17:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 18537 invoked by uid 89); 11 Sep 2014 13:16:59 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-we0-f174.google.com Received: from mail-we0-f174.google.com (HELO mail-we0-f174.google.com) (74.125.82.174) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Thu, 11 Sep 2014 13:16:57 +0000 Received: by mail-we0-f174.google.com with SMTP id t60so5617677wes.5 for ; Thu, 11 Sep 2014 06:16:52 -0700 (PDT) X-Received: by 10.194.84.175 with SMTP id a15mr1516359wjz.12.1410441409342; Thu, 11 Sep 2014 06:16:49 -0700 (PDT) Received: from msticlxl57.ims.intel.com ([192.55.55.41]) by mx.google.com with ESMTPSA id ll20sm1527657wic.14.2014.09.11.06.16.46 for (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 11 Sep 2014 06:16:48 -0700 (PDT) Date: Thu, 11 Sep 2014 17:16:27 +0400 From: Kirill Yukhin To: Uros Bizjak Cc: Jakub Jelinek , Richard Henderson , GCC Patches , kirill.yukhin@gmail.com Subject: [PATCH i386 AVX512] [38/n] Extend vpternlog, valign, vrotate insn patterns. Message-ID: <20140911131626.GC62005@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Hello, Patch in the bottom extends patterns for rotate, ternlog and align. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/sse.md (define_mode_iterator VI48_AVX512VL): New. (define_expand "_vternlog_maskz"): Rename from "avx512f_vternlog_maskz" and update mode iterator. (define_insn "_vternlog"): Rename from "avx512f_vternlog" and update mode iterator. (define_insn "_vternlog_mask"): Rename from "avx512f_vternlog_mask" and update mode iterator. (define_insn "_align"): Rename from "avx512f_align" and update mode iterator. (define_insn "_v"): Rename from "avx512f_v" and update mode iterator. (define_insn "_"): Rename from "avx512f_" and update mode iterator. (define_insn "clz2"): Use VI48_AVX512VL. (define_insn "conflict"): Ditto. --- Thanks, K diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 92f94b9..73bdd22 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -7158,27 +7158,27 @@ [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_expand "avx512f_vternlog_maskz" - [(match_operand:VI48_512 0 "register_operand") - (match_operand:VI48_512 1 "register_operand") - (match_operand:VI48_512 2 "register_operand") - (match_operand:VI48_512 3 "nonimmediate_operand") +(define_expand "_vternlog_maskz" + [(match_operand:VI48_AVX512VL 0 "register_operand") + (match_operand:VI48_AVX512VL 1 "register_operand") + (match_operand:VI48_AVX512VL 2 "register_operand") + (match_operand:VI48_AVX512VL 3 "nonimmediate_operand") (match_operand:SI 4 "const_0_to_255_operand") (match_operand: 5 "register_operand")] "TARGET_AVX512F" { - emit_insn (gen_avx512f_vternlog_maskz_1 ( + emit_insn (gen__vternlog_maskz_1 ( operands[0], operands[1], operands[2], operands[3], operands[4], CONST0_RTX (mode), operands[5])); DONE; }) -(define_insn "avx512f_vternlog" - [(set (match_operand:VI48_512 0 "register_operand" "=v") - (unspec:VI48_512 - [(match_operand:VI48_512 1 "register_operand" "0") - (match_operand:VI48_512 2 "register_operand" "v") - (match_operand:VI48_512 3 "nonimmediate_operand" "vm") +(define_insn "_vternlog" + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (unspec:VI48_AVX512VL + [(match_operand:VI48_AVX512VL 1 "register_operand" "0") + (match_operand:VI48_AVX512VL 2 "register_operand" "v") + (match_operand:VI48_AVX512VL 3 "nonimmediate_operand" "vm") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_VTERNLOG))] "TARGET_AVX512F" @@ -7187,13 +7187,13 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_vternlog_mask" - [(set (match_operand:VI48_512 0 "register_operand" "=v") - (vec_merge:VI48_512 - (unspec:VI48_512 - [(match_operand:VI48_512 1 "register_operand" "0") - (match_operand:VI48_512 2 "register_operand" "v") - (match_operand:VI48_512 3 "nonimmediate_operand" "vm") +(define_insn "_vternlog_mask" + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI48_AVX512VL + (unspec:VI48_AVX512VL + [(match_operand:VI48_AVX512VL 1 "register_operand" "0") + (match_operand:VI48_AVX512VL 2 "register_operand" "v") + (match_operand:VI48_AVX512VL 3 "nonimmediate_operand" "vm") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_VTERNLOG) (match_dup 1) @@ -7227,12 +7227,12 @@ [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_align" - [(set (match_operand:VI48_512 0 "register_operand" "=v") - (unspec:VI48_512 [(match_operand:VI48_512 1 "register_operand" "v") - (match_operand:VI48_512 2 "nonimmediate_operand" "vm") - (match_operand:SI 3 "const_0_to_255_operand")] - UNSPEC_ALIGN))] +(define_insn "_align" + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (unspec:VI48_AVX512VL [(match_operand:VI48_AVX512VL 1 "register_operand" "v") + (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm") + (match_operand:SI 3 "const_0_to_255_operand")] + UNSPEC_ALIGN))] "TARGET_AVX512F" "valign\t{%3, %2, %1, %0|%0, %1, %2, %3}"; [(set_attr "prefix" "evex") @@ -9430,20 +9430,20 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) -(define_insn "avx512f_v" - [(set (match_operand:VI48_512 0 "register_operand" "=v") - (any_rotate:VI48_512 - (match_operand:VI48_512 1 "register_operand" "v") - (match_operand:VI48_512 2 "nonimmediate_operand" "vm")))] +(define_insn "_v" + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (any_rotate:VI48_AVX512VL + (match_operand:VI48_AVX512VL 1 "register_operand" "v") + (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")))] "TARGET_AVX512F" "vpv\t{%2, %1, %0|%0, %1, %2}" [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_" - [(set (match_operand:VI48_512 0 "register_operand" "=v") - (any_rotate:VI48_512 - (match_operand:VI48_512 1 "nonimmediate_operand" "vm") +(define_insn "_" + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (any_rotate:VI48_AVX512VL + (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "vm") (match_operand:SI 2 "const_0_to_255_operand")))] "TARGET_AVX512F" "vp\t{%2, %1, %0|%0, %1, %2}" @@ -17011,9 +17011,9 @@ (set_attr "mode" "")]) (define_insn "clz2" - [(set (match_operand:VI48_512 0 "register_operand" "=v") - (clz:VI48_512 - (match_operand:VI48_512 1 "nonimmediate_operand" "vm")))] + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (clz:VI48_AVX512VL + (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "vm")))] "TARGET_AVX512CD" "vplzcnt\t{%1, %0|%0, %1}" [(set_attr "type" "sse") @@ -17021,9 +17021,9 @@ (set_attr "mode" "")]) (define_insn "conflict" - [(set (match_operand:VI48_512 0 "register_operand" "=v") - (unspec:VI48_512 - [(match_operand:VI48_512 1 "nonimmediate_operand" "vm")] + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (unspec:VI48_AVX512VL + [(match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "vm")] UNSPEC_CONFLICT))] "TARGET_AVX512CD" "vpconflict\t{%1, %0|%0, %1}"