From patchwork Tue Sep 9 11:41:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 387291 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6DCA31400B5 for ; Tue, 9 Sep 2014 21:42:07 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=BH/ZL7yKt+aM3FiXN /jKJwKeD8b0kDf9egZ/Pjxi0TnR40txMgd8XGA1WnnjGkmFjfZ5+VPVvHmmZqIuj xOkqaVoHvLS8ovOlXZUwT0hIpOp5szFixJDVBswR41kTsogtHUbSVcXTwJbMos5g dqq3kSJz6SPG78Joxa6PKwvq6c= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=gFAUW2c4G2xBEn/H+JDor84 mV/k=; b=OCHNhtWiPbPl6KkNj/V4s3q9Vo/Y1CflYcOXZDJtQPwcDpcDTqzyBoa PD0jB8ANWiVTJlH9gTnwekl6TMNR1cNOrDDJQM3OsXz56gtohX3JWYq/anHrLZLJ GoAh+fDx7QlpZkYNJ4zhp/SmAgNEpmdEDI1M81Gun+Wvfxc1ifzw= Received: (qmail 4759 invoked by alias); 9 Sep 2014 11:42:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 4750 invoked by uid 89); 9 Sep 2014 11:42:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-we0-f182.google.com Received: from mail-we0-f182.google.com (HELO mail-we0-f182.google.com) (74.125.82.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 09 Sep 2014 11:41:58 +0000 Received: by mail-we0-f182.google.com with SMTP id k48so1323783wev.13 for ; Tue, 09 Sep 2014 04:41:55 -0700 (PDT) X-Received: by 10.194.221.74 with SMTP id qc10mr41534130wjc.39.1410262915694; Tue, 09 Sep 2014 04:41:55 -0700 (PDT) Received: from msticlxl57.ims.intel.com ([192.55.55.41]) by mx.google.com with ESMTPSA id z8sm15261702wiv.24.2014.09.09.04.41.53 for (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 09 Sep 2014 04:41:55 -0700 (PDT) Date: Tue, 9 Sep 2014 15:41:35 +0400 From: Kirill Yukhin To: Uros Bizjak Cc: Jakub Jelinek , Richard Henderson , GCC Patches Subject: Re: [PATCH i386 AVX512] [32/n] Add reduce,range,fpclass. Message-ID: <20140909114134.GB62820@msticlxl57.ims.intel.com> References: <20140829135525.GD18938@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes On 30 Aug 10:21, Uros Bizjak wrote: Hello, > It looks to me that _SCALAR unspecs are redundant, and should be > possible to use UNSPEC_REDUCE for all patterns without unwanted > matching. Updated patch in the bottom gcc/ * config/i386/i386.c (ix86_expand_args_builtin): Handle avx512dq_rangepv8df_mask_round, avx512dq_rangepv16sf_mask_round, avx512dq_rangepv4df_mask, avx512dq_rangepv8sf_mask, avx512dq_rangepv2df_mask, avx512dq_rangepv4sf_mask. * config/i386/sse.md (define_c_enum "unspec"): Add UNSPEC_REDUCE, UNSPEC_FPCLASS, UNSPEC_RANGE. (define_insn "reducep"): New. (define_insn "reduces"): New. (define_insn "avx512dq_rangep"): New. (define_insn "avx512dq_ranges"): New. (define_insn "avx512dq_fpclass"): New. (define_insn "avx512dq_vmfpclass"): New. Bootstrapped. Is it ok for trunk? --- Thanks, K diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index ff37ffe..15cdb5e 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -34114,6 +34114,12 @@ ix86_expand_args_builtin (const struct builtin_description *d, case CODE_FOR_avx512vl_getmantv4df_mask: case CODE_FOR_avx512vl_getmantv4sf_mask: case CODE_FOR_avx512vl_getmantv2df_mask: + case CODE_FOR_avx512dq_rangepv8df_mask_round: + case CODE_FOR_avx512dq_rangepv16sf_mask_round: + case CODE_FOR_avx512dq_rangepv4df_mask: + case CODE_FOR_avx512dq_rangepv8sf_mask: + case CODE_FOR_avx512dq_rangepv2df_mask: + case CODE_FOR_avx512dq_rangepv4sf_mask: error ("the last argument must be a 4-bit immediate"); return const0_rtx; diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 1706e4c..78276b7 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -128,6 +128,11 @@ UNSPEC_SHA256MSG1 UNSPEC_SHA256MSG2 UNSPEC_SHA256RNDS2 + + ;; For AVX512DQ support + UNSPEC_REDUCE + UNSPEC_FPCLASS + UNSPEC_RANGE ]) (define_c_enum "unspecv" [ @@ -2330,6 +2335,34 @@ DONE; }) +(define_insn "reducep" + [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") + (unspec:VF_AVX512VL + [(match_operand:VF_AVX512VL 1 "nonimmediate_operand" "vm") + (match_operand:SI 2 "const_0_to_255_operand")] + UNSPEC_REDUCE))] + "TARGET_AVX512DQ" + "vreduce\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "sse") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "reduces" + [(set (match_operand:VF_128 0 "register_operand" "=v") + (vec_merge:VF_128 + (unspec:VF_128 + [(match_operand:VF_128 1 "register_operand" "v") + (match_operand:VF_128 2 "nonimmediate_operand" "vm") + (match_operand:SI 3 "const_0_to_255_operand")] + UNSPEC_REDUCE) + (match_dup 1) + (const_int 1)))] + "TARGET_AVX512DQ" + "vreduce\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "type" "sse") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel floating point comparisons @@ -16754,6 +16787,63 @@ (set_attr "memory" "none,load") (set_attr "mode" "")]) +(define_insn "avx512dq_rangep" + [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") + (unspec:VF_AVX512VL + [(match_operand:VF_AVX512VL 1 "register_operand" "v") + (match_operand:VF_AVX512VL 2 "" "") + (match_operand:SI 3 "const_0_to_15_operand")] + UNSPEC_RANGE))] + "TARGET_AVX512DQ && " + "vrange\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "type" "sse") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512dq_ranges" + [(set (match_operand:VF_128 0 "register_operand" "=v") + (vec_merge:VF_128 + (unspec:VF_128 + [(match_operand:VF_128 1 "register_operand" "v") + (match_operand:VF_128 2 "" "") + (match_operand:SI 3 "const_0_to_15_operand")] + UNSPEC_RANGE) + (match_dup 1) + (const_int 1)))] + "TARGET_AVX512DQ" + "vrange\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "type" "sse") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512dq_fpclass" + [(set (match_operand: 0 "register_operand" "=Yk") + (unspec: + [(match_operand:VF_AVX512VL 1 "register_operand" "v") + (match_operand:QI 2 "const_0_to_255_operand" "n")] + UNSPEC_FPCLASS))] + "TARGET_AVX512DQ" + "vfpclass\t{%2, %1, %0|%0, %1, %2}"; + [(set_attr "type" "sse") + (set_attr "length_immediate" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512dq_vmfpclass" + [(set (match_operand: 0 "register_operand" "=Yk") + (and: + (unspec: + [(match_operand:VF_128 1 "register_operand" "v") + (match_operand:QI 2 "const_0_to_255_operand" "n")] + UNSPEC_FPCLASS) + (const_int 1)))] + "TARGET_AVX512DQ" + "vfpclass\t{%2, %1, %0|%0, %1, %2}"; + [(set_attr "type" "sse") + (set_attr "length_immediate" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "_getmant" [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") (unspec:VF_AVX512VL