From patchwork Wed Aug 20 12:51:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 381666 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 296141400E4 for ; Wed, 20 Aug 2014 22:52:19 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:content-transfer-encoding:in-reply-to; q=dns; s= default; b=MU391DLVZKmtYbzoRJGdJDQZ5tvWrgOWr8GLafi1Z6SKqoBFU1EpZ eoYL/2HQLz4K1AqLxx2cpg9JxF4DGkkAdKWPVReEYhYRF0MIwAsCjTWtQEKkNwCZ 4b+6PZviK+WTJU/NYFFHKHfOs43QzwQewa0dEl3gYr3zMibfW258lE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:content-transfer-encoding:in-reply-to; s=default; bh=qqJqtKHnsB1ZLmKpAna/39HYgUM=; b=C2kTl2CGaaqZYC7+wKsSzMyZyQML iC0IAPtIG3bg2wZXDw8hWtJJ0b37E0U/Wv3dsphmsukSWS8X22Pd2+2LW8LYYa2H XknHRkv+p/nQSV9QVR4NbDqltCg0B9M+7QoroLYswAMuAuBet6F+iAhUfwZPx2y/ nfSWe2wFwp1+JcE= Received: (qmail 13858 invoked by alias); 20 Aug 2014 12:52:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 13843 invoked by uid 89); 20 Aug 2014 12:52:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wg0-f47.google.com Received: from mail-wg0-f47.google.com (HELO mail-wg0-f47.google.com) (74.125.82.47) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 20 Aug 2014 12:52:04 +0000 Received: by mail-wg0-f47.google.com with SMTP id b13so7721639wgh.18 for ; Wed, 20 Aug 2014 05:52:01 -0700 (PDT) X-Received: by 10.180.80.165 with SMTP id s5mr14591683wix.61.1408539121919; Wed, 20 Aug 2014 05:52:01 -0700 (PDT) Received: from msticlxl57.ims.intel.com (jfdmzpr04-ext.jf.intel.com. [134.134.137.73]) by mx.google.com with ESMTPSA id vm1sm9588172wjc.14.2014.08.20.05.51.59 for (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Aug 2014 05:52:01 -0700 (PDT) Date: Wed, 20 Aug 2014 16:51:52 +0400 From: Kirill Yukhin To: Uros Bizjak Cc: Jakub Jelinek , Richard Henderson , GCC Patches Subject: Re: [PATCH i386 AVX512] [19/n] Extends AVX-512 broadcasts. Message-ID: <20140820125150.GB37280@msticlxl57.ims.intel.com> References: <20140815115159.GE35144@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Hello Uroš, On 15 Aug 20:29, Uros Bizjak wrote: > Can you avoid insn constraints like: > > > + "TARGET_AVX512DQ && ( == 64 || TARGET_AVX512VL)" > > This should be split to two insn patterns, each with different > baseline insn constraint. I've splitted pattern into two similar w/ different mode iterators. Bootstrapped and avx512-regtested. Is it ok for trunk? gcc/ * config/i386/sse.md (define_mode_iterator VI4F_BRCST32x2): New. (define_mode_attr 64x2mode): Ditto. (define_mode_attr 32x2mode): Ditto. (define_insn "avx512dq_broadcast" with VI4F_BRCST32x2 mode iterator): Ditto. (define_insn "avx512vl_broadcast_1"): Ditto. (define_insn "avx512dq_broadcast_1" with V16FI mode iterator): Ditto. (define_insn "avx512dq_broadcast_1" with VI8F_512 mode iterator): Ditto. (define_insn "avx512dq_broadcast_1" with VI8F_256 mode iterator): Ditto. --- Thanks, K diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 4632b3a..6a5faee 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -482,6 +482,7 @@ (define_mode_iterator VI8F_128 [V2DI V2DF]) (define_mode_iterator VI4F_256 [V8SI V8SF]) (define_mode_iterator VI8F_256 [V4DI V4DF]) +(define_mode_iterator VI8F_512 [V8DI V8DF]) (define_mode_iterator VI8F_256_512 [V4DI V4DF (V8DI "TARGET_AVX512F") (V8DF "TARGET_AVX512F")]) (define_mode_iterator VI48F_256_512 @@ -14514,6 +14515,83 @@ (set_attr "prefix" "vex") (set_attr "mode" "")]) +;; For broadcast[i|f]32x2. Yes there is no v4sf version, only v4si. +(define_mode_iterator VI4F_BRCST32x2 + [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + V16SF (V8SF "TARGET_AVX512VL")]) + +(define_mode_attr 64x2mode + [(V8DF "V2DF") (V8DI "V2DI") (V4DI "V2DI") (V4DF "V2DF")]) + +(define_mode_attr 32x2mode + [(V16SF "V2SF") (V16SI "V2SI") (V8SI "V2SI") + (V8SF "V2SF") (V4SI "V2SI")]) + +(define_insn "avx512dq_broadcast" + [(set (match_operand:VI4F_BRCST32x2 0 "register_operand" "=v") + (vec_duplicate:VI4F_BRCST32x2 + (vec_select:<32x2mode> + (match_operand: 1 "nonimmediate_operand" "vm") + (parallel [(const_int 0) (const_int 1)]))))] + "TARGET_AVX512DQ" + "vbroadcast32x2\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512vl_broadcast_1" + [(set (match_operand:VI4F_256 0 "register_operand" "=v,v") + (vec_duplicate:VI4F_256 + (match_operand: 1 "nonimmediate_operand" "v,m")))] + "TARGET_AVX512VL" + "@ + vshuf32x4\t{$0x0, %t1, %t1, %0|%0, %t1, %t1, 0x0} + vbroadcast32x4\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512dq_broadcast_1" + [(set (match_operand:V16FI 0 "register_operand" "=v,v") + (vec_duplicate:V16FI + (match_operand: 1 "nonimmediate_operand" "v,m")))] + "TARGET_AVX512DQ" + "@ + vshuf32x4\t{$0x44, %g1, %g1, %0|%0, %g1, %g1, 0x44} + vbroadcast32x8\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512dq_broadcast_1" + [(set (match_operand:VI8F_512 0 "register_operand" "=v,v") + (vec_duplicate:VI8F_512 + (match_operand:<64x2mode> 1 "nonimmediate_operand" "v,m")))] + "TARGET_AVX512DQ" + "@ + vshuf64x2\t{$0x0, %g1, %g1, %0|%0, %g1, %g1, 0x0} + vbroadcast64x2\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512dq_broadcast_1" + [(set (match_operand:VI8F_256 0 "register_operand" "=v,v") + (vec_duplicate:VI8F_256 + (match_operand:<64x2mode> 1 "nonimmediate_operand" "v,m")))] + "TARGET_AVX512DQ && TARGET_AVX512VL" + "@ + vshuf64x2\t{$0x0, %t1, %t1, %0|%0, %t1, %t1, 0x0} + vbroadcast64x2\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "avx512cd_maskb_vec_dup" [(set (match_operand:VI8_AVX512VL 0 "register_operand" "=v") (vec_duplicate:VI8_AVX512VL