diff mbox

[i386,AVX512,20/n] AVX-512 integer shift pattern.

Message ID 20140815115600.GF35144@msticlxl57.ims.intel.com
State New
Headers show

Commit Message

Kirill Yukhin Aug. 15, 2014, 11:56 a.m. UTC 
Hello,
This patch extends shift pattern to support AVX-512
new insn.

Bootstrapped.
New tests on top of patch-set all pass
under simulator.

Is it ok for trunk?

gcc/
	* config/i386/sse.md
	(define_mode_iterator VI248_AVX2): Add V32HI mode.
	(define_insn "<shift_insn><mode>3<mask_name>"): Add masking.

--
Thanks, K

Comments

Uros Bizjak Aug. 15, 2014, 6:35 p.m. UTC | #1 
On Fri, Aug 15, 2014 at 1:56 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Hello,
> This patch extends shift pattern to support AVX-512
> new insn.
>
> Bootstrapped.
> New tests on top of patch-set all pass
> under simulator.
>
> Is it ok for trunk?
>
> gcc/
>         * config/i386/sse.md
>         (define_mode_iterator VI248_AVX2): Add V32HI mode.
>         (define_insn "<shift_insn><mode>3<mask_name>"): Add masking.

Again, please split insn pattern to avoid:

+  "TARGET_SSE2
+   && <mask_mode512bit_condition>
+   && ((<MODE>mode != V16HImode && <MODE>mode != V8HImode)
+       || TARGET_AVX512BW
+       || !<mask_applied>)"

insn constraints. The insn constraint should use baseline TARGET_* and
mode iterator should use TARGET_* that results in "baseline TARGET_ &&
iterator TARGET_" for certain mode. If these are properly used, then
there is no need to use <MODE>mode checks in the insn constraint.

Uros.
diff mbox

Patch

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index a8c7ba8..c219523 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -348,7 +348,7 @@ 
    (V8SI "TARGET_AVX2") V4SI])
 
 (define_mode_iterator VI248_AVX2
-  [(V16HI "TARGET_AVX2") V8HI
+  [(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI
    (V8SI "TARGET_AVX2") V4SI
    (V4DI "TARGET_AVX2") V2DI])
 
@@ -8552,15 +8552,19 @@ 
        (const_string "0")))
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "<shift_insn><mode>3"
-  [(set (match_operand:VI248_AVX2 0 "register_operand" "=x,x")
+(define_insn "<shift_insn><mode>3<mask_name>"
+  [(set (match_operand:VI248_AVX2 0 "register_operand" "=x,v")
 	(any_lshift:VI248_AVX2
-	  (match_operand:VI248_AVX2 1 "register_operand" "0,x")
-	  (match_operand:SI 2 "nonmemory_operand" "xN,xN")))]
-  "TARGET_SSE2"
+	  (match_operand:VI248_AVX2 1 "register_operand" "0,v")
+	  (match_operand:SI 2 "nonmemory_operand" "xN,vN")))]
+  "TARGET_SSE2
+   && <mask_mode512bit_condition>
+   && ((<MODE>mode != V16HImode && <MODE>mode != V8HImode)
+       || TARGET_AVX512BW
+       || !<mask_applied>)"
   "@
    p<vshift><ssemodesuffix>\t{%2, %0|%0, %2}
-   vp<vshift><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+   vp<vshift><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
   [(set_attr "isa" "noavx,avx")
    (set_attr "type" "sseishft")
    (set (attr "length_immediate")