From patchwork Sun Jan 26 14:01:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allan Sandfeld Jensen X-Patchwork-Id: 314177 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A7CAD2C007A for ; Mon, 27 Jan 2014 01:02:14 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:references:in-reply-to:mime-version :content-type:message-id; q=dns; s=default; b=NqPkznzUpp2SuBtPkD S29Z5zEzojj27g1S59zDB4+oOuCKdkU36JTS+PQMcDJllMkM/Y28SeLPWsGZUDId dgUHOx05VBwjG76hphBufLrPUrvio5TwX2MagJNRHVNuHpwntxjBs3P2VqSBgQCn m4+RjIRPsQZJqgPvHo8WcKbl4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:references:in-reply-to:mime-version :content-type:message-id; s=default; bh=mucJ4166LFQ3P7m3Ag1p0XXx 0Vk=; b=v1JUEdslTHwMgS0nKCCOtf7313Fc5OzPFbA3rOkyUDhg+NlgmfaUqNvq 66sngEIer/dsVSeNnLVez+b2nOs/uOTIdRyOIsBbFrS4c8JrjYcDSGw52clyFv8M lhbEKthnY6apyvVgIaNl+CrQvPK2wxULg/MmS5e/+fus7vs9aVE= Received: (qmail 6009 invoked by alias); 26 Jan 2014 14:02:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5994 invoked by uid 89); 26 Jan 2014 14:02:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-bk0-f52.google.com Received: from mail-bk0-f52.google.com (HELO mail-bk0-f52.google.com) (209.85.214.52) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Sun, 26 Jan 2014 14:02:05 +0000 Received: by mail-bk0-f52.google.com with SMTP id e11so2295367bkh.39 for ; Sun, 26 Jan 2014 06:02:02 -0800 (PST) X-Received: by 10.204.164.15 with SMTP id c15mr18426853bky.22.1390744921989; Sun, 26 Jan 2014 06:02:01 -0800 (PST) Received: from princessluna.localnet (p57A05F4E.dip0.t-ipconnect.de. [87.160.95.78]) by mx.google.com with ESMTPSA id rf10sm10033823bkb.3.2014.01.26.06.01.59 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 26 Jan 2014 06:02:00 -0800 (PST) From: Allan Sandfeld Jensen To: "gcc-patches@gcc.gnu.org" Subject: Re: [Patch, i386] Separate Intel processor with expanded ISA Date: Sun, 26 Jan 2014 15:01:54 +0100 User-Agent: KMail/1.13.7 (Linux/3.12-1-amd64; KDE/4.12.1; x86_64; ; ) References: <201312290015.14676.linux@carewolf.com> In-Reply-To: <201312290015.14676.linux@carewolf.com> MIME-Version: 1.0 Message-Id: <201401261501.54321.linux@carewolf.com> X-IsSubscribed: yes Updated patch with test. diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ccbea0f..e80c30b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2013-12-29 Allan Sandfeld Jensen + * config/i386/i386.c (get_builtin_code_for_version): Separate + Westmere from Nehalem, Ivy Bridge from Sandy Bridge and + Broadwell from Haswell. + 2014-01-25 Walter Lee * config/tilegx/sync.md (atomic_fetch_sub): Fix negation and diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index cf79486..50f3624 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -31298,18 +31298,27 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) priority = P_PROC_SSSE3; break; case PROCESSOR_NEHALEM: - /* We translate "arch=corei7" and "arch=nehelam" to - "corei7" so that it will be mapped to M_INTEL_COREI7 - as cpu type to cover all M_INTEL_COREI7_XXXs. */ - arg_str = "corei7"; + if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AES) + arg_str = "westmere"; + else + /* We translate "arch=corei7" and "arch=nehelam" to + "corei7" so that it will be mapped to M_INTEL_COREI7 + as cpu type to cover all M_INTEL_COREI7_XXXs. */ + arg_str = "corei7"; priority = P_PROC_SSE4_2; break; case PROCESSOR_SANDYBRIDGE: - arg_str = "sandybridge"; + if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_F16C) + arg_str = "ivybridge"; + else + arg_str = "sandybridge"; priority = P_PROC_AVX; break; case PROCESSOR_HASWELL: - arg_str = "haswell"; + if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_ADX) + arg_str = "broadwell"; + else + arg_str = "haswell"; priority = P_PROC_AVX2; break; case PROCESSOR_BONNELL: diff --git a/gcc/testsuite/g++.dg/ext/mv16.C b/gcc/testsuite/g++.dg/ext/mv16.C new file mode 100644 index 0000000..4737c79 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/mv16.C @@ -0,0 +1,69 @@ +// Test that dispatching can choose the right multiversion +// for Intel CPUs with the same internal GCC processor id +// but slighly different sets of x86 extensions. + +// { dg-do run { target i?86-*-* x86_64-*-* } } +// { dg-require-ifunc "" } +// { dg-options "-O2" } + +#include + +int __attribute__ ((target("default"))) +foo () +{ + return 0; +} + +int __attribute__ ((target("arch=nehalem"))) +foo () +{ + return 4; +} + +int __attribute__ ((target("arch=westmere"))) +foo () +{ + return 5; +} + +int __attribute__ ((target("arch=sandybridge"))) +foo () +{ + return 8; +} + +int __attribute__ ((target("arch=ivybridge"))) +foo () +{ + return 9; +} + +int __attribute__ ((target("arch=haswell"))) +foo () +{ + return 12; +} + +int main () +{ + int val = foo (); + + if (__builtin_cpu_is ("nehalem")) + assert (val == 4); + else + if (__builtin_cpu_is ("westmere")) + assert (val == 5); + else + if (__builtin_cpu_is ("sandybridge")) + assert (val == 8); + else + if (__builtin_cpu_is ("ivybridge")) + assert (val == 9); + else + if (__builtin_cpu_is ("haswell")) + assert (val == 12); + else + assert (val == 0); + + return 0; +}