From patchwork Wed Dec 18 13:02:08 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 302878 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 317F62C00A7 for ; Thu, 19 Dec 2013 00:02:29 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=iSHb6lsVdiXcdpUrl 0BCwImxPEFBbNMJLJFqfY4oBtBPt8oC5KxVFegAN0h3M7xU6o5yonmZYJtLZL9+Y hrQNWO9GiHWoig3V/mC/Zy2ecy7z/6UkeCAvKdpS7epa3c66mCzbi0PU7aMvgvaH 3vXPeosPWg6f6+XNxDfk1IfwxI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=xDI2ysjyrkBSVCOmLStk8XN M1NU=; b=K51cl7vij1bapOkbLEXc5eDsCWU9EwCaJIcTkqbvxp65l3NabEUVOl8 rok2A3MGghGo5jtLZv8tFL210e2iNpwVW8spQv+4d0saL8Z9J9iU7lF5jcj2Ih14 AORyt7jrteqUD2PpHosPUYDMYTRzOxLmSyiiWwwQmw2Cm3mww1zU= Received: (qmail 32391 invoked by alias); 18 Dec 2013 13:02:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 32379 invoked by uid 89); 18 Dec 2013 13:02:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pb0-f52.google.com Received: from mail-pb0-f52.google.com (HELO mail-pb0-f52.google.com) (209.85.160.52) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 18 Dec 2013 13:02:19 +0000 Received: by mail-pb0-f52.google.com with SMTP id uo5so8418993pbc.39 for ; Wed, 18 Dec 2013 05:02:17 -0800 (PST) X-Received: by 10.66.235.106 with SMTP id ul10mr33827804pac.19.1387371737562; Wed, 18 Dec 2013 05:02:17 -0800 (PST) Received: from msticlxl57.ims.intel.com (fmdmzpr01-ext.fm.intel.com. [192.55.54.36]) by mx.google.com with ESMTPSA id m2sm41028160pbn.19.2013.12.18.05.02.14 for (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Dec 2013 05:02:16 -0800 (PST) Date: Wed, 18 Dec 2013 16:02:08 +0300 From: Kirill Yukhin To: rth@redhat.com, Uros Bizjak , Jakub Jelinek , law@redhat.com Cc: GCC Patches Subject: Re: [PATCH i386 4/8] [AVX512] [6/8] Add substed patterns: `sae' subst. Message-ID: <20131218130208.GC57860@msticlxl57.ims.intel.com> References: <20130814074404.GE52726@msticlxl57.ims.intel.com> <20131106072126.GC23881@msticlxl57.ims.intel.com> <20131115170731.GE45205@msticlxl57.ims.intel.com> <20131119091142.GE25998@msticlxl57.ims.intel.com> <20131202131027.GC2453@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20131202131027.GC2453@msticlxl57.ims.intel.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Hello, On 02 Dec 16:10, Kirill Yukhin wrote: > Hello, > On 19 Nov 12:11, Kirill Yukhin wrote: > > Hello, > > On 15 Nov 20:07, Kirill Yukhin wrote: > > > > Is it ok for trunk? > > > Ping. > > Ping. > Ping. Ping. Rebased patch in the bottom. --- Thanks, K --- gcc/config/i386/sse.md | 168 +++++++++++++++++++++++------------------------ gcc/config/i386/subst.md | 31 +++++++++ 2 files changed, 115 insertions(+), 84 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 23edbd3..5b10cec 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1523,45 +1523,45 @@ ;; isn't really correct, as those rtl operators aren't defined when ;; applied to NaNs. Hopefully the optimizers won't get too smart on us. -(define_expand "3" +(define_expand "3" [(set (match_operand:VF 0 "register_operand") (smaxmin:VF (match_operand:VF 1 "nonimmediate_operand") (match_operand:VF 2 "nonimmediate_operand")))] - "TARGET_SSE && " + "TARGET_SSE && && " { if (!flag_finite_math_only) operands[1] = force_reg (mode, operands[1]); ix86_fixup_binary_operands_no_copy (, mode, operands); }) -(define_insn "*3_finite" +(define_insn "*3_finite" [(set (match_operand:VF 0 "register_operand" "=x,v") (smaxmin:VF (match_operand:VF 1 "nonimmediate_operand" "%0,v") - (match_operand:VF 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VF 2 "nonimmediate_operand" "xm,")))] "TARGET_SSE && flag_finite_math_only && ix86_binary_operator_ok (, mode, operands) - && " + && && " "@ \t{%2, %0|%0, %2} - v\t{%2, %1, %0|%0, %1, %2}" + v\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseadd") (set_attr "btver2_sse_attr" "maxmin") (set_attr "prefix" "") (set_attr "mode" "")]) -(define_insn "*3" +(define_insn "*3" [(set (match_operand:VF 0 "register_operand" "=x,v") (smaxmin:VF (match_operand:VF 1 "register_operand" "0,v") - (match_operand:VF 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VF 2 "nonimmediate_operand" "xm,")))] "TARGET_SSE && !flag_finite_math_only - && " + && && " "@ \t{%2, %0|%0, %2} - v\t{%2, %1, %0|%0, %1, %2}" + v\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseadd") (set_attr "btver2_sse_attr" "maxmin") @@ -2099,15 +2099,15 @@ [(V16SF "const_0_to_31_operand") (V8DF "const_0_to_31_operand") (V16SI "const_0_to_7_operand") (V8DI "const_0_to_7_operand")]) -(define_insn "avx512f_cmp3" +(define_insn "avx512f_cmp3" [(set (match_operand: 0 "register_operand" "=k") (unspec: [(match_operand:VI48F_512 1 "register_operand" "v") - (match_operand:VI48F_512 2 "nonimmediate_operand" "vm") + (match_operand:VI48F_512 2 "nonimmediate_operand" "") (match_operand:SI 3 "" "n")] UNSPEC_PCMP))] - "TARGET_AVX512F" - "vcmp\t{%3, %2, %1, %0|%0, %1, %2, %3}" + "TARGET_AVX512F && " + "vcmp\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssecmp") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") @@ -2127,35 +2127,35 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_vmcmp3" +(define_insn "avx512f_vmcmp3" [(set (match_operand: 0 "register_operand" "=k") (and: (unspec: [(match_operand:VF_128 1 "register_operand" "v") - (match_operand:VF_128 2 "nonimmediate_operand" "vm") + (match_operand:VF_128 2 "nonimmediate_operand" "") (match_operand:SI 3 "const_0_to_31_operand" "n")] UNSPEC_PCMP) (const_int 1)))] "TARGET_AVX512F" - "vcmp\t{%3, %2, %1, %0|%0, %1, %2, %3}" + "vcmp\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssecmp") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_vmcmp3_mask" +(define_insn "avx512f_vmcmp3_mask" [(set (match_operand: 0 "register_operand" "=k") (and: (unspec: [(match_operand:VF_128 1 "register_operand" "v") - (match_operand:VF_128 2 "nonimmediate_operand" "vm") + (match_operand:VF_128 2 "nonimmediate_operand" "") (match_operand:SI 3 "const_0_to_31_operand" "n")] UNSPEC_PCMP) (and: (match_operand: 4 "register_operand" "k") (const_int 1))))] "TARGET_AVX512F" - "vcmp\t{%3, %2, %1, %0%{%4%}|%0%{%4%}, %1, %2, %3}" + "vcmp\t{%3, %2, %1, %0%{%4%}|%0%{%4%}, %1, %2, %3}" [(set_attr "type" "ssecmp") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") @@ -2173,17 +2173,17 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "_comi" +(define_insn "_comi" [(set (reg:CCFP FLAGS_REG) (compare:CCFP (vec_select:MODEF (match_operand: 0 "register_operand" "v") (parallel [(const_int 0)])) (vec_select:MODEF - (match_operand: 1 "nonimmediate_operand" "vm") + (match_operand: 1 "nonimmediate_operand" "") (parallel [(const_int 0)]))))] "SSE_FLOAT_MODE_P (mode)" - "%vcomi\t{%1, %0|%0, %1}" + "%vcomi\t{%1, %0|%0, %1}" [(set_attr "type" "ssecomi") (set_attr "prefix" "maybe_vex") (set_attr "prefix_rep" "0") @@ -2193,17 +2193,17 @@ (const_string "0"))) (set_attr "mode" "")]) -(define_insn "_ucomi" +(define_insn "_ucomi" [(set (reg:CCFPU FLAGS_REG) (compare:CCFPU (vec_select:MODEF (match_operand: 0 "register_operand" "v") (parallel [(const_int 0)])) (vec_select:MODEF - (match_operand: 1 "nonimmediate_operand" "vm") + (match_operand: 1 "nonimmediate_operand" "") (parallel [(const_int 0)]))))] "SSE_FLOAT_MODE_P (mode)" - "%vucomi\t{%1, %0|%0, %1}" + "%vucomi\t{%1, %0|%0, %1}" [(set_attr "type" "ssecomi") (set_attr "prefix" "maybe_vex") (set_attr "prefix_rep" "0") @@ -3379,14 +3379,14 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "DI")]) -(define_insn "sse_cvttss2si" +(define_insn "sse_cvttss2si" [(set (match_operand:SI 0 "register_operand" "=r,r") (fix:SI (vec_select:SF - (match_operand:V4SF 1 "nonimmediate_operand" "v,m") + (match_operand:V4SF 1 "nonimmediate_operand" "v,") (parallel [(const_int 0)]))))] "TARGET_SSE" - "%vcvttss2si\t{%1, %0|%0, %k1}" + "%vcvttss2si\t{%1, %0|%0, %k1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "amdfam10_decode" "double,double") @@ -3395,14 +3395,14 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "SI")]) -(define_insn "sse_cvttss2siq" +(define_insn "sse_cvttss2siq" [(set (match_operand:DI 0 "register_operand" "=r,r") (fix:DI (vec_select:SF - (match_operand:V4SF 1 "nonimmediate_operand" "v,vm") + (match_operand:V4SF 1 "nonimmediate_operand" "v,") (parallel [(const_int 0)]))))] "TARGET_SSE && TARGET_64BIT" - "%vcvttss2si{q}\t{%1, %0|%0, %k1}" + "%vcvttss2si{q}\t{%1, %0|%0, %k1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "amdfam10_decode" "double,double") @@ -3511,12 +3511,12 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "fix_truncv16sfv16si2" +(define_insn "fix_truncv16sfv16si2" [(set (match_operand:V16SI 0 "register_operand" "=v") (any_fix:V16SI - (match_operand:V16SF 1 "nonimmediate_operand" "vm")))] + (match_operand:V16SF 1 "nonimmediate_operand" "")))] "TARGET_AVX512F" - "vcvttps2dq\t{%1, %0|%0, %1}" + "vcvttps2dq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "XI")]) @@ -3672,26 +3672,26 @@ (set_attr "prefix" "evex") (set_attr "mode" "DI")]) -(define_insn "avx512f_vcvttss2usi" +(define_insn "avx512f_vcvttss2usi" [(set (match_operand:SI 0 "register_operand" "=r") (unsigned_fix:SI (vec_select:SF - (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (match_operand:V4SF 1 "nonimmediate_operand" "") (parallel [(const_int 0)]))))] "TARGET_AVX512F" - "vcvttss2usi\t{%1, %0|%0, %1}" + "vcvttss2usi\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "SI")]) -(define_insn "avx512f_vcvttss2usiq" +(define_insn "avx512f_vcvttss2usiq" [(set (match_operand:DI 0 "register_operand" "=r") (unsigned_fix:DI (vec_select:SF - (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (match_operand:V4SF 1 "nonimmediate_operand" "") (parallel [(const_int 0)]))))] "TARGET_AVX512F && TARGET_64BIT" - "vcvttss2usi\t{%1, %0|%0, %1}" + "vcvttss2usi\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "DI")]) @@ -3722,26 +3722,26 @@ (set_attr "prefix" "evex") (set_attr "mode" "DI")]) -(define_insn "avx512f_vcvttsd2usi" +(define_insn "avx512f_vcvttsd2usi" [(set (match_operand:SI 0 "register_operand" "=r") (unsigned_fix:SI (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "vm") + (match_operand:V2DF 1 "nonimmediate_operand" "") (parallel [(const_int 0)]))))] "TARGET_AVX512F" - "vcvttsd2usi\t{%1, %0|%0, %1}" + "vcvttsd2usi\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "SI")]) -(define_insn "avx512f_vcvttsd2usiq" +(define_insn "avx512f_vcvttsd2usiq" [(set (match_operand:DI 0 "register_operand" "=r") (unsigned_fix:DI (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "vm") + (match_operand:V2DF 1 "nonimmediate_operand" "") (parallel [(const_int 0)]))))] "TARGET_AVX512F && TARGET_64BIT" - "vcvttsd2usi\t{%1, %0|%0, %1}" + "vcvttsd2usi\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "DI")]) @@ -3807,14 +3807,14 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "DI")]) -(define_insn "sse2_cvttsd2si" +(define_insn "sse2_cvttsd2si" [(set (match_operand:SI 0 "register_operand" "=r,r") (fix:SI (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "v,m") + (match_operand:V2DF 1 "nonimmediate_operand" "v,") (parallel [(const_int 0)]))))] "TARGET_SSE2" - "%vcvttsd2si\t{%1, %0|%0, %q1}" + "%vcvttsd2si\t{%1, %0|%0, %q1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "amdfam10_decode" "double,double") @@ -3824,14 +3824,14 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "SI")]) -(define_insn "sse2_cvttsd2siq" +(define_insn "sse2_cvttsd2siq" [(set (match_operand:DI 0 "register_operand" "=r,r") (fix:DI (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "v,m") + (match_operand:V2DF 1 "nonimmediate_operand" "v,") (parallel [(const_int 0)]))))] "TARGET_SSE2 && TARGET_64BIT" - "%vcvttsd2si{q}\t{%1, %0|%0, %q1}" + "%vcvttsd2si{q}\t{%1, %0|%0, %q1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "amdfam10_decode" "double,double") @@ -3991,12 +3991,12 @@ (set_attr "prefix" "evex") (set_attr "mode" "OI")]) -(define_insn "fix_truncv8dfv8si2" +(define_insn "fix_truncv8dfv8si2" [(set (match_operand:V8SI 0 "register_operand" "=v") (any_fix:V8SI - (match_operand:V8DF 1 "nonimmediate_operand" "vm")))] + (match_operand:V8DF 1 "nonimmediate_operand" "")))] "TARGET_AVX512F" - "vcvttpd2dq\t{%1, %0|%0, %1}" + "vcvttpd2dq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "OI")]) @@ -4157,12 +4157,12 @@ (define_mode_attr sf2dfmode [(V8DF "V8SF") (V4DF "V4SF")]) -(define_insn "_cvtps2pd" +(define_insn "_cvtps2pd" [(set (match_operand:VF2_512_256 0 "register_operand" "=v") (float_extend:VF2_512_256 - (match_operand: 1 "nonimmediate_operand" "vm")))] - "TARGET_AVX && " - "vcvtps2pd\t{%1, %0|%0, %1}" + (match_operand: 1 "nonimmediate_operand" "")))] + "TARGET_AVX && && " + "vcvtps2pd\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) @@ -6532,12 +6532,12 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_getexp" +(define_insn "avx512f_getexp" [(set (match_operand:VF_512 0 "register_operand" "=v") - (unspec:VF_512 [(match_operand:VF_512 1 "nonimmediate_operand" "vm")] + (unspec:VF_512 [(match_operand:VF_512 1 "nonimmediate_operand" "")] UNSPEC_GETEXP))] "TARGET_AVX512F" - "vgetexp\t{%1, %0|%0, %1}"; + "vgetexp\t{%1, %0|%0, %1}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -6613,32 +6613,32 @@ DONE; }) -(define_insn "avx512f_fixupimm" +(define_insn "avx512f_fixupimm" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 [(match_operand:VF_512 1 "register_operand" "0") (match_operand:VF_512 2 "register_operand" "v") - (match_operand: 3 "nonimmediate_operand" "vm") + (match_operand: 3 "nonimmediate_operand" "") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_FIXUPIMM))] "TARGET_AVX512F" - "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; + "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_fixupimm_mask" +(define_insn "avx512f_fixupimm_mask" [(set (match_operand:VF_512 0 "register_operand" "=v") (vec_merge:VF_512 (unspec:VF_512 [(match_operand:VF_512 1 "register_operand" "0") (match_operand:VF_512 2 "register_operand" "v") - (match_operand: 3 "nonimmediate_operand" "vm") + (match_operand: 3 "nonimmediate_operand" "") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_FIXUPIMM) (match_dup 1) (match_operand: 5 "register_operand" "k")))] "TARGET_AVX512F" - "vfixupimm\t{%4, %3, %2, %0%{%5%}|%0%{%5%}, %2, %3, %4}"; + "vfixupimm\t{%4, %3, %2, %0%{%5%}|%0%{%5%}, %2, %3, %4}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -6657,30 +6657,30 @@ DONE; }) -(define_insn "avx512f_sfixupimm" +(define_insn "avx512f_sfixupimm" [(set (match_operand:VF_128 0 "register_operand" "=v") (vec_merge:VF_128 (unspec:VF_128 [(match_operand:VF_128 1 "register_operand" "0") (match_operand:VF_128 2 "register_operand" "v") - (match_operand: 3 "nonimmediate_operand" "vm") + (match_operand: 3 "nonimmediate_operand" "") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_FIXUPIMM) (match_dup 1) (const_int 1)))] "TARGET_AVX512F" - "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; + "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_sfixupimm_mask" +(define_insn "avx512f_sfixupimm_mask" [(set (match_operand:VF_128 0 "register_operand" "=v") (vec_merge:VF_128 (vec_merge:VF_128 (unspec:VF_128 [(match_operand:VF_128 1 "register_operand" "0") (match_operand:VF_128 2 "register_operand" "v") - (match_operand: 3 "nonimmediate_operand" "vm") + (match_operand: 3 "nonimmediate_operand" "") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_FIXUPIMM) (match_dup 1) @@ -6688,18 +6688,18 @@ (match_dup 1) (match_operand: 5 "register_operand" "k")))] "TARGET_AVX512F" - "vfixupimm\t{%4, %3, %2, %0%{%5%}|%0%{%5%}, %2, %3, %4}"; + "vfixupimm\t{%4, %3, %2, %0%{%5%}|%0%{%5%}, %2, %3, %4}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_rndscale" +(define_insn "avx512f_rndscale" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 - [(match_operand:VF_512 1 "nonimmediate_operand" "vm") + [(match_operand:VF_512 1 "nonimmediate_operand" "") (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_ROUND))] "TARGET_AVX512F" - "vrndscale\t{%2, %1, %0|%0, %1, %2}" + "vrndscale\t{%2, %1, %0|%0, %1, %2}" [(set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -14574,13 +14574,13 @@ (set_attr "btver2_decode" "double") (set_attr "mode" "V8SF")]) -(define_insn "avx512f_vcvtph2ps512" +(define_insn "avx512f_vcvtph2ps512" [(set (match_operand:V16SF 0 "register_operand" "=v") (unspec:V16SF - [(match_operand:V16HI 1 "nonimmediate_operand" "vm")] + [(match_operand:V16HI 1 "nonimmediate_operand" "")] UNSPEC_VCVTPH2PS))] "TARGET_AVX512F" - "vcvtph2ps\t{%1, %0|%0, %1}" + "vcvtph2ps\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "V16SF")]) @@ -15079,14 +15079,14 @@ (set_attr "memory" "none,load") (set_attr "mode" "")]) -(define_insn "avx512f_getmant" +(define_insn "avx512f_getmant" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 - [(match_operand:VF_512 1 "nonimmediate_operand" "vm") + [(match_operand:VF_512 1 "nonimmediate_operand" "") (match_operand:SI 2 "const_0_to_15_operand")] UNSPEC_GETMANT))] "TARGET_AVX512F" - "vgetmant\t{%2, %1, %0|%0, %1, %2}"; + "vgetmant\t{%2, %1, %0|%0, %1, %2}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index 76c183c..0887f14 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -128,3 +128,34 @@ (set (match_dup 0) (match_dup 1)) (unspec [(match_operand:SI 2 "const_0_to_4_operand")] UNSPEC_EMBEDDED_ROUNDING)])]) + +(define_subst_attr "round_saeonly_name" "round_saeonly" "" "_round") +(define_subst_attr "round_saeonly_mask_operand2" "mask" "%R2" "%R4") +(define_subst_attr "round_saeonly_mask_operand3" "mask" "%R3" "%R5") +(define_subst_attr "round_saeonly_mask_scalar_operand3" "mask_scalar" "%R3" "%R5") +(define_subst_attr "round_saeonly_mask_scalar_operand4" "mask_scalar" "%R4" "%R6") +(define_subst_attr "round_saeonly_mask_scalar_merge_operand4" "mask_scalar_merge" "%R4" "%R5") +(define_subst_attr "round_saeonly_sd_mask_operand5" "sd" "%R5" "%R7") +(define_subst_attr "round_saeonly_op2" "round_saeonly" "" "%R2") +(define_subst_attr "round_saeonly_op4" "round_saeonly" "" "%R4") +(define_subst_attr "round_saeonly_op5" "round_saeonly" "" "%R5") +(define_subst_attr "round_saeonly_op6" "round_saeonly" "" "%R6") +(define_subst_attr "round_saeonly_mask_op2" "round_saeonly" "" "") +(define_subst_attr "round_saeonly_mask_op3" "round_saeonly" "" "") +(define_subst_attr "round_saeonly_mask_scalar_op3" "round_saeonly" "" "") +(define_subst_attr "round_saeonly_mask_scalar_op4" "round_saeonly" "" "") +(define_subst_attr "round_saeonly_mask_scalar_merge_op4" "round_saeonly" "" "") +(define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "") +(define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v") +(define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v") +(define_subst_attr "round_saeonly_mode512bit_condition" "round_saeonly" "1" "(GET_MODE (operands[0]) == V16SFmode || GET_MODE (operands[0]) == V8DFmode)") +(define_subst_attr "round_saeonly_mode512bit_condition_op1" "round_saeonly" "1" "(GET_MODE (operands[1]) == V16SFmode || GET_MODE (operands[1]) == V8DFmode)") + +(define_subst "round_saeonly" + [(set (match_operand:SUBST_A 0) + (match_operand:SUBST_A 1))] + "TARGET_AVX512F" + [(parallel[ + (set (match_dup 0) + (match_dup 1)) + (unspec [(match_operand:SI 2 "const_4_to_5_operand")] UNSPEC_EMBEDDED_ROUNDING)])])