From patchwork Wed Dec 4 20:01:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jakub Jelinek X-Patchwork-Id: 296621 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 660322C007E for ; Thu, 5 Dec 2013 07:01:34 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=Au6cjBfSAQAvlDGI4 94w8JRkqbYOzmizU3TWZpvHZpQkB7nwSclrg9KqD2w596taXrfAzBxp8OQnU0dIp 0i3fQpbzx1jU2dQEgt5e8KPjVXvrk7o2XWFWMj2dJYFPFLJ8DtMiu1oTbzFIi/ka LoKw90Hc9WyTw3rcdyBBSkv0Sk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:references:mime-version :content-type:in-reply-to; s=default; bh=kcDA1g7z1oEseYhI13sLGR8 rzUM=; b=f1egD1XGu/QxQFzR86leWY5PzPXtfwMYs1Fav4OgFUYuOFcKPnZhHYS cpTqxNoGhCcEkWVqFPO687d1iIQSppo98vSmuRAMlLXBXDiC7Frf6Pz0VlpVxFti WtNOGxwqLeHrW3slWXkaj9uU1q6u6DvTSuF/CgNFgqudq2llXEcE= Received: (qmail 11206 invoked by alias); 4 Dec 2013 20:01:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 11191 invoked by uid 89); 4 Dec 2013 20:01:24 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL, BAYES_50, RDNS_NONE, SPF_HELO_PASS, SPF_PASS, URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: mx1.redhat.com Received: from Unknown (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 04 Dec 2013 20:01:23 +0000 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id rB4K1Dds006669 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 4 Dec 2013 15:01:14 -0500 Received: from tucnak.zalov.cz (vpn1-4-55.ams2.redhat.com [10.36.4.55]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id rB4K1Bdi003155 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 4 Dec 2013 15:01:12 -0500 Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.14.7/8.14.7) with ESMTP id rB4K1AmB023630; Wed, 4 Dec 2013 21:01:10 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.14.7/8.14.7/Submit) id rB4K1AjS023629; Wed, 4 Dec 2013 21:01:10 +0100 Date: Wed, 4 Dec 2013 21:01:09 +0100 From: Jakub Jelinek To: Uros Bizjak Cc: Marek Polacek , GCC Patches Subject: Re: [PATCH 2/2] Implement -fsanitize=signed-integer-overflow (i?86 parts) Message-ID: <20131204200109.GZ892@tucnak.redhat.com> Reply-To: Jakub Jelinek References: <20131204134418.GD32420@redhat.com> <20131204190745.GY892@tucnak.redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes On Wed, Dec 04, 2013 at 08:23:22PM +0100, Uros Bizjak wrote: > > My memory is fuzzy about that, but I think that was my first version which > > didn't work, because with match_dup then it requires on the internal-fn.c > > side to pass 4 arguments instead of just 3. I can try again though. Weird, now it works, dunno what I have done differently before. Though, I've discovered a bug in internal-fn.c for the negation case. So is this everything you wanted? 2013-12-04 Jakub Jelinek Marek Polacek * config/i386/i386.md (DWI, dwi): Add QImode and HImode cases. (addv4, subv4, mulv4, negv3): New expanders. (*addv4, *subv4, *mulv4, *negv3): New insns. * internal-fn.c (ubsan_expand_si_overflow_neg_check): The return value lives in res rather than target. Jakub --- gcc/config/i386/i386.md.jj 2013-12-04 12:05:46.689185140 +0100 +++ gcc/config/i386/i386.md 2013-12-04 20:40:25.417309596 +0100 @@ -905,8 +905,8 @@ (define_mode_iterator DWI [(DI "!TARGET_ (TI "TARGET_64BIT")]) ;; Double word integer modes as mode attribute. -(define_mode_attr DWI [(SI "DI") (DI "TI")]) -(define_mode_attr dwi [(SI "di") (DI "ti")]) +(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")]) +(define_mode_attr dwi [(QI "hi") (HI "si") (SI "di") (DI "ti")]) ;; Half mode for double word integer modes. (define_mode_iterator DWIH [(SI "!TARGET_64BIT") @@ -6160,6 +6160,41 @@ (define_insn "*addqi_ext_2" [(set_attr "type" "alu") (set_attr "mode" "QI")]) +;; Add with jump on overflow. +(define_expand "addv4" + [(parallel [(set (reg:CCO FLAGS_REG) + (eq:CCO (plus: + (sign_extend: + (match_operand:SWI 1 "nonimmediate_operand")) + (sign_extend: + (match_operand:SWI 2 ""))) + (sign_extend: + (plus:SWI (match_dup 1) (match_dup 2))))) + (set (match_operand:SWI 0 "register_operand") + (plus:SWI (match_dup 1) (match_dup 2)))]) + (set (pc) (if_then_else + (eq (reg:CCO FLAGS_REG) (const_int 0)) + (label_ref (match_operand 3)) + (pc)))] + "" + "ix86_fixup_binary_operands_no_copy (PLUS, mode, operands);") + +(define_insn "*addv4" + [(set (reg:CCO FLAGS_REG) + (eq:CCO (plus: + (sign_extend: + (match_operand:SWI 1 "nonimmediate_operand" "%0,0")) + (sign_extend: + (match_operand:SWI 2 "" ","))) + (sign_extend: + (plus:SWI (match_dup 1) (match_dup 2))))) + (set (match_operand:SWI 0 "nonimmediate_operand" "=,m") + (plus:SWI (match_dup 1) (match_dup 2)))] + "ix86_binary_operator_ok (PLUS, mode, operands)" + "add{}\t{%2, %0|%0, %2}" + [(set_attr "type" "alu") + (set_attr "mode" "")]) + ;; The lea patterns for modes less than 32 bits need to be matched by ;; several insns converted to real lea by splitters. @@ -6397,6 +6432,41 @@ (define_insn "*subsi_2_zext" [(set_attr "type" "alu") (set_attr "mode" "SI")]) +;; Subtract with jump on overflow. +(define_expand "subv4" + [(parallel [(set (reg:CCO FLAGS_REG) + (eq:CCO (minus: + (sign_extend: + (match_operand:SWI 1 "nonimmediate_operand")) + (sign_extend: + (match_operand:SWI 2 ""))) + (sign_extend: + (minus:SWI (match_dup 1) (match_dup 2))))) + (set (match_operand:SWI 0 "register_operand") + (minus:SWI (match_dup 1) (match_dup 2)))]) + (set (pc) (if_then_else + (eq (reg:CCO FLAGS_REG) (const_int 0)) + (label_ref (match_operand 3)) + (pc)))] + "" + "ix86_fixup_binary_operands_no_copy (MINUS, mode, operands);") + +(define_insn "*subv4" + [(set (reg:CCO FLAGS_REG) + (eq:CCO (minus: + (sign_extend: + (match_operand:SWI 1 "nonimmediate_operand" "0,0")) + (sign_extend: + (match_operand:SWI 2 "" ",m"))) + (sign_extend: + (minus:SWI (match_dup 1) (match_dup 2))))) + (set (match_operand:SWI 0 "nonimmediate_operand" "=m,") + (minus:SWI (match_dup 1) (match_dup 2)))] + "ix86_binary_operator_ok (MINUS, mode, operands)" + "sub{}\t{%2, %0|%0, %2}" + [(set_attr "type" "alu") + (set_attr "mode" "")]) + (define_insn "*sub_3" [(set (reg FLAGS_REG) (compare (match_operand:SWI 1 "nonimmediate_operand" "0,0") @@ -6711,6 +6781,58 @@ (define_insn "*mulqi3_1" (set_attr "bdver1_decode" "direct") (set_attr "mode" "QI")]) +;; Multiply with jump on overflow. +(define_expand "mulv4" + [(parallel [(set (reg:CCO FLAGS_REG) + (eq:CCO (mult: + (sign_extend: + (match_operand:SWI48 1 "register_operand")) + (sign_extend: + (match_operand:SWI48 2 ""))) + (sign_extend: + (mult:SWI48 (match_dup 1) (match_dup 2))))) + (set (match_operand:SWI48 0 "register_operand") + (mult:SWI48 (match_dup 1) (match_dup 2)))]) + (set (pc) (if_then_else + (eq (reg:CCO FLAGS_REG) (const_int 0)) + (label_ref (match_operand 3)) + (pc)))]) + +(define_insn "*mulv4" + [(set (reg:CCO FLAGS_REG) + (eq:CCO (mult: + (sign_extend: + (match_operand:SWI 1 "nonimmediate_operand" "%rm,rm,0")) + (sign_extend: + (match_operand:SWI 2 "" "K,,mr"))) + (sign_extend: + (mult:SWI (match_dup 1) (match_dup 2))))) + (set (match_operand:SWI 0 "register_operand" "=r,r,r") + (mult:SWI (match_dup 1) (match_dup 2)))] + "!(MEM_P (operands[1]) && MEM_P (operands[2]))" + "@ + imul{}\t{%2, %1, %0|%0, %1, %2} + imul{}\t{%2, %1, %0|%0, %1, %2} + imul{}\t{%2, %0|%0, %2}" + [(set_attr "type" "imul") + (set_attr "prefix_0f" "0,0,1") + (set (attr "athlon_decode") + (cond [(eq_attr "cpu" "athlon") + (const_string "vector") + (eq_attr "alternative" "1") + (const_string "vector") + (and (eq_attr "alternative" "2") + (match_operand 1 "memory_operand")) + (const_string "vector")] + (const_string "direct"))) + (set (attr "amdfam10_decode") + (cond [(and (eq_attr "alternative" "0,1") + (match_operand 1 "memory_operand")) + (const_string "vector")] + (const_string "direct"))) + (set_attr "bdver1_decode" "direct") + (set_attr "mode" "")]) + (define_expand "mul3" [(parallel [(set (match_operand: 0 "register_operand") (mult: @@ -8624,6 +8746,36 @@ (define_insn "*negsi2_cmpz_zext" [(set_attr "type" "negnot") (set_attr "mode" "SI")]) +;; Negate with jump on overflow. +(define_expand "negv3" + [(parallel [(set (reg:CCO FLAGS_REG) + (ne:CCO (match_operand:SWI 1 "register_operand") + (match_dup 3))) + (set (match_operand:SWI 0 "register_operand") + (neg:SWI (match_dup 1)))]) + (set (pc) (if_then_else + (eq (reg:CCO FLAGS_REG) (const_int 0)) + (label_ref (match_operand 2)) + (pc)))] + "" +{ + operands[3] + = gen_int_mode (HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1), + mode); +}) + +(define_insn "*negv3" + [(set (reg:CCO FLAGS_REG) + (ne:CCO (match_operand:SWI 1 "nonimmediate_operand" "0") + (match_operand:SWI 2 "const_int_operand"))) + (set (match_operand:SWI 0 "nonimmediate_operand" "=m") + (neg:SWI (match_dup 1)))] + "ix86_unary_operator_ok (NEG, mode, operands) + && mode_signbit_p (mode, operands[2])" + "neg{}\t%0" + [(set_attr "type" "negnot") + (set_attr "mode" "")]) + ;; Changing of sign for FP values is doable using integer unit too. (define_expand "2" --- gcc/internal-fn.c.jj 2013-12-04 20:09:39.000000000 +0100 +++ gcc/internal-fn.c 2013-12-04 20:54:40.994939539 +0100 @@ -291,7 +291,6 @@ ubsan_expand_si_overflow_neg_check (gimp && !find_reg_note (last, REG_BR_PROB, 0)) add_int_reg_note (last, REG_BR_PROB, PROB_VERY_UNLIKELY); emit_jump (done_label); - res = target; } else {