From patchwork Wed Oct 16 16:06:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 283995 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 053CE2C00C8 for ; Thu, 17 Oct 2013 03:07:10 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=oE+xVQXZe+IPl7zk5qfXeZQdlCzYrlz7ZwozJfiEW4D6slC0ul porwTuMwP7RsnipkpdjgOx66vyEgL3eF79vmr6W3kie4u4E+Dam0ixp6nhfC2PU2 XzOEpbdYwKjwgnYB1H6qyJKmtoVsYovvKH7I6SajcGtwMsWugAKPsI358= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=qgtyrrkpQH8s2ZQZHRxBMKMMjLM=; b=crhX0GjOwvsIDWq2o2YW SMdutqqkikjfiQysgF2G5VMdgYPvoKK+s83NPIhrk9wwPHYfS9yH4zf/cpuB52mu LkKb/cL+opqlPYwRjMMHepomnb9ybN4cMQa3kheVxFVFIc249uVDdKaAUnqL+FLD xDh+GGLLMSrBtnh7wQFzSVA= Received: (qmail 16241 invoked by alias); 16 Oct 2013 16:07:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 16220 invoked by uid 89); 16 Oct 2013 16:07:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pb0-f43.google.com Received: from mail-pb0-f43.google.com (HELO mail-pb0-f43.google.com) (209.85.160.43) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 16 Oct 2013 16:07:02 +0000 Received: by mail-pb0-f43.google.com with SMTP id md4so1013356pbc.2 for ; Wed, 16 Oct 2013 09:07:00 -0700 (PDT) X-Received: by 10.66.163.2 with SMTP id ye2mr3644650pab.170.1381939619978; Wed, 16 Oct 2013 09:06:59 -0700 (PDT) Received: from msticlxl57.ims.intel.com (fmdmzpr03-ext.fm.intel.com. [192.55.54.38]) by mx.google.com with ESMTPSA id ve9sm92068592pbc.19.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 16 Oct 2013 09:06:58 -0700 (PDT) Date: Wed, 16 Oct 2013 20:06:21 +0400 From: Kirill Yukhin To: Uros Bizjak Cc: GCC Patches Subject: [PATCH i386 AVX2] Remove redundant expands. Message-ID: <20131016160621.GB22220@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Hello, It seems that gang of AVX* patterns were copy and pasted from SSE, however as far as they are NDD, we may remove corresponding expands which sort operands. ChangeLog: * config/i386/sse.md (vec_widen_umult_even_v8si): Remove expand, make insn visible, remove redundant check. (vec_widen_smult_even_v8si): Ditto. (avx2_pmaddwd): Ditto. (avx2_eq3): Ditto. (avx512f_eq3): Ditto. Bootrstrap pass. All AVX* tests pass. Is it ok to commit to main trunk? --- Thanks, K --- gcc/ChangeLog | 9 ++++ gcc/config/i386/sse.md | 119 ++++++------------------------------------------- 2 files changed, 23 insertions(+), 105 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ebaa3e0..b25d8eb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2013-10-16 Kirill Yukhin + + * config/i386/sse.md (vec_widen_umult_even_v8si): Remove expand, + make insn visible, remove redundant check. + (vec_widen_smult_even_v8si): Ditto. + (avx2_pmaddwd): Ditto. + (avx2_eq3): Ditto. + (avx512f_eq3): Ditto. + 2013-10-16 Yvan Roux * config/arm/arm.opt (mlra): New option. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 2046dd5..57e4c2b 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -6067,23 +6067,7 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) -(define_expand "vec_widen_umult_even_v8si" - [(set (match_operand:V4DI 0 "register_operand") - (mult:V4DI - (zero_extend:V4DI - (vec_select:V4SI - (match_operand:V8SI 1 "nonimmediate_operand") - (parallel [(const_int 0) (const_int 2) - (const_int 4) (const_int 6)]))) - (zero_extend:V4DI - (vec_select:V4SI - (match_operand:V8SI 2 "nonimmediate_operand") - (parallel [(const_int 0) (const_int 2) - (const_int 4) (const_int 6)])))))] - "TARGET_AVX2" - "ix86_fixup_binary_operands_no_copy (MULT, V8SImode, operands);") - -(define_insn "*vec_widen_umult_even_v8si" +(define_insn "vec_widen_umult_even_v8si" [(set (match_operand:V4DI 0 "register_operand" "=x") (mult:V4DI (zero_extend:V4DI @@ -6096,7 +6080,7 @@ (match_operand:V8SI 2 "nonimmediate_operand" "xm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))))] - "TARGET_AVX2 && ix86_binary_operator_ok (MULT, V8SImode, operands)" + "TARGET_AVX2" "vpmuludq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseimul") (set_attr "prefix" "vex") @@ -6137,28 +6121,12 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) -(define_expand "vec_widen_smult_even_v8si" - [(set (match_operand:V4DI 0 "register_operand") - (mult:V4DI - (sign_extend:V4DI - (vec_select:V4SI - (match_operand:V8SI 1 "nonimmediate_operand") - (parallel [(const_int 0) (const_int 2) - (const_int 4) (const_int 6)]))) - (sign_extend:V4DI - (vec_select:V4SI - (match_operand:V8SI 2 "nonimmediate_operand") - (parallel [(const_int 0) (const_int 2) - (const_int 4) (const_int 6)])))))] - "TARGET_AVX2" - "ix86_fixup_binary_operands_no_copy (MULT, V8SImode, operands);") - -(define_insn "*vec_widen_smult_even_v8si" +(define_insn "vec_widen_smult_even_v8si" [(set (match_operand:V4DI 0 "register_operand" "=x") (mult:V4DI (sign_extend:V4DI (vec_select:V4SI - (match_operand:V8SI 1 "nonimmediate_operand" "x") + (match_operand:V8SI 1 "nonimmediate_operand" "%x") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (sign_extend:V4DI @@ -6166,7 +6134,7 @@ (match_operand:V8SI 2 "nonimmediate_operand" "xm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))))] - "TARGET_AVX2 && ix86_binary_operator_ok (MULT, V8SImode, operands)" + "TARGET_AVX2" "vpmuldq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "avx") (set_attr "type" "sseimul") @@ -6210,41 +6178,7 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) -(define_expand "avx2_pmaddwd" - [(set (match_operand:V8SI 0 "register_operand") - (plus:V8SI - (mult:V8SI - (sign_extend:V8SI - (vec_select:V8HI - (match_operand:V16HI 1 "nonimmediate_operand") - (parallel [(const_int 0) (const_int 2) - (const_int 4) (const_int 6) - (const_int 8) (const_int 10) - (const_int 12) (const_int 14)]))) - (sign_extend:V8SI - (vec_select:V8HI - (match_operand:V16HI 2 "nonimmediate_operand") - (parallel [(const_int 0) (const_int 2) - (const_int 4) (const_int 6) - (const_int 8) (const_int 10) - (const_int 12) (const_int 14)])))) - (mult:V8SI - (sign_extend:V8SI - (vec_select:V8HI (match_dup 1) - (parallel [(const_int 1) (const_int 3) - (const_int 5) (const_int 7) - (const_int 9) (const_int 11) - (const_int 13) (const_int 15)]))) - (sign_extend:V8SI - (vec_select:V8HI (match_dup 2) - (parallel [(const_int 1) (const_int 3) - (const_int 5) (const_int 7) - (const_int 9) (const_int 11) - (const_int 13) (const_int 15)]))))))] - "TARGET_AVX2" - "ix86_fixup_binary_operands_no_copy (MULT, V16HImode, operands);") - -(define_insn "*avx2_pmaddwd" +(define_insn "avx2_pmaddwd" [(set (match_operand:V8SI 0 "register_operand" "=x") (plus:V8SI (mult:V8SI @@ -6275,7 +6209,7 @@ (const_int 5) (const_int 7) (const_int 9) (const_int 11) (const_int 13) (const_int 15)]))))))] - "TARGET_AVX2 && ix86_binary_operator_ok (MULT, V16HImode, operands)" + "TARGET_AVX2" "vpmaddwd\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix" "vex") @@ -6618,20 +6552,12 @@ [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_expand "3" - [(set (match_operand:VI124_256_48_512 0 "register_operand") - (maxmin:VI124_256_48_512 - (match_operand:VI124_256_48_512 1 "nonimmediate_operand") - (match_operand:VI124_256_48_512 2 "nonimmediate_operand")))] - "TARGET_AVX2" - "ix86_fixup_binary_operands_no_copy (, mode, operands);") - -(define_insn "*avx2_3" +(define_insn "3" [(set (match_operand:VI124_256_48_512 0 "register_operand" "=v") (maxmin:VI124_256_48_512 (match_operand:VI124_256_48_512 1 "nonimmediate_operand" "%v") (match_operand:VI124_256_48_512 2 "nonimmediate_operand" "vm")))] - "TARGET_AVX2 && ix86_binary_operator_ok (, mode, operands)" + "TARGET_AVX2" "vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_extra" "1") @@ -6830,42 +6756,25 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_expand "avx2_eq3" - [(set (match_operand:VI_256 0 "register_operand") - (eq:VI_256 - (match_operand:VI_256 1 "nonimmediate_operand") - (match_operand:VI_256 2 "nonimmediate_operand")))] - "TARGET_AVX2" - "ix86_fixup_binary_operands_no_copy (EQ, mode, operands);") - -(define_insn "*avx2_eq3" +(define_insn "avx2_eq3" [(set (match_operand:VI_256 0 "register_operand" "=x") (eq:VI_256 (match_operand:VI_256 1 "nonimmediate_operand" "%x") (match_operand:VI_256 2 "nonimmediate_operand" "xm")))] - "TARGET_AVX2 && ix86_binary_operator_ok (EQ, mode, operands)" + "TARGET_AVX2" "vpcmpeq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecmp") (set_attr "prefix_extra" "1") (set_attr "prefix" "vex") (set_attr "mode" "OI")]) -(define_expand "avx512f_eq3" - [(set (match_operand: 0 "register_operand") - (unspec: - [(match_operand:VI48_512 1 "register_operand") - (match_operand:VI48_512 2 "nonimmediate_operand")] - UNSPEC_MASKED_EQ))] - "TARGET_AVX512F" - "ix86_fixup_binary_operands_no_copy (EQ, mode, operands);") - -(define_insn "avx512f_eq3_1" +(define_insn "avx512f_eq3" [(set (match_operand: 0 "register_operand" "=k") (unspec: - [(match_operand:VI48_512 1 "register_operand" "%v") + [(match_operand:VI48_512 1 "nonimmediate_operand" "%v") (match_operand:VI48_512 2 "nonimmediate_operand" "vm")] UNSPEC_MASKED_EQ))] - "TARGET_AVX512F && ix86_binary_operator_ok (EQ, mode, operands)" + "TARGET_AVX512F" "vpcmpeq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecmp") (set_attr "prefix_extra" "1")