From patchwork Wed Oct 9 10:25:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 281791 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AE7AC2C0087 for ; Wed, 9 Oct 2013 21:26:26 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=pSlwgFzelck2CxqvJ SgNU0ggVHq1xCWgdcAstsMwmspXpIXMN5HwsLLOjHZH0M5NOWsofnEKpVFuPhMzx /4eLZgLvdduQrgdPtjpsOG33Z1uzLZOmxqHsTnYF5S2pscXQSoTk/k5YVmQ0vSLC 3kMznv2Pse/UnQD/x2NfDI/sMM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=ubDivpRkFS5kQsob1hf9pPL wVuU=; b=I/4NGumLEBY9AZKke8PNF/lAX/SgOe40QlTCdXtGO2HGjPYXT5eMr1M +SIt4IdSDag+EfGzmSB7tCsptaZg3RxvZTskfTos1KlRNd4pCfly9409qrH7IyWY m6ePG+jVZRy6i6X+2+PUouWKNwo6ty34DGnYG9kDo2Nyou/EHsA8= Received: (qmail 8483 invoked by alias); 9 Oct 2013 10:26:17 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 8474 invoked by uid 89); 9 Oct 2013 10:26:16 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pd0-f182.google.com Received: from mail-pd0-f182.google.com (HELO mail-pd0-f182.google.com) (209.85.192.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 09 Oct 2013 10:26:16 +0000 Received: by mail-pd0-f182.google.com with SMTP id r10so712514pdi.27 for ; Wed, 09 Oct 2013 03:26:14 -0700 (PDT) X-Received: by 10.66.250.138 with SMTP id zc10mr8837317pac.72.1381314374248; Wed, 09 Oct 2013 03:26:14 -0700 (PDT) Received: from msticlxl57.ims.intel.com ([192.55.54.40]) by mx.google.com with ESMTPSA id ef10sm53888638pac.1.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 09 Oct 2013 03:26:13 -0700 (PDT) Date: Wed, 9 Oct 2013 14:25:38 +0400 From: Kirill Yukhin To: Richard Henderson Cc: Uros Bizjak , Vladimir Makarov , Jakub Jelinek , GCC Patches Subject: Re: [PATCH i386 3/8] [AVX512] [5/n] Add AVX-512 patterns: Introduce `multdiv' code iterator. Message-ID: <20131009102538.GD52466@msticlxl57.ims.intel.com> References: <20130808112524.GA40277@msticlxl57.ims.intel.com> <20130814072638.GD52726@msticlxl57.ims.intel.com> <52129604.6040305@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <52129604.6040305@redhat.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Hello, > This patch is still far too large. > > I think you should split it up based on every single mode iterator that > you need to add or change. Here's 5th subpatch. It introduces `multdiv' code iterator. Is it Ok? Testing: 1. Bootstrap pass. 2. make check shows no regressions. 3. Spec 2000 & 2006 build show no regressions both with and without -mavx512f option. 4. Spec 2000 & 2006 run shows no stability regressions without -mavx512f option. --- Thanks, K PS. If it is Ok - I am going to strip out ChangeLog lines from big patch. --- gcc/config/i386/i386.md | 4 ++++ gcc/config/i386/sse.md | 31 +++++++------------------------ 2 files changed, 11 insertions(+), 24 deletions(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index cc332ea..10ca6cb 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -746,6 +746,8 @@ (define_code_iterator sat_plusminus [ss_plus us_plus ss_minus us_minus]) +(define_code_iterator multdiv [mult div]) + ;; Base name for define_insn (define_code_attr plusminus_insn [(plus "add") (ss_plus "ssadd") (us_plus "usadd") @@ -757,6 +759,8 @@ (minus "sub") (ss_minus "subs") (us_minus "subus")]) (define_code_attr plusminus_carry_mnemonic [(plus "adc") (minus "sbb")]) +(define_code_attr multdiv_mnemonic + [(mult "mul") (div "div")]) ;; Mark commutative operators as such in constraints. (define_code_attr comm [(plus "%") (ss_plus "%") (us_plus "%") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index cdb9ae0..89c31c5 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1061,21 +1061,22 @@ (set_attr "btver2_decode" "direct,double") (set_attr "mode" "")]) -(define_insn "_vmmul3" +(define_insn "_vm3" [(set (match_operand:VF_128 0 "register_operand" "=x,v") (vec_merge:VF_128 - (mult:VF_128 + (multdiv:VF_128 (match_operand:VF_128 1 "register_operand" "0,v") (match_operand:VF_128 2 "nonimmediate_operand" "xm,vm")) (match_dup 1) (const_int 1)))] "TARGET_SSE" "@ - mul\t{%2, %0|%0, %2} - vmul\t{%2, %1, %0|%0, %1, %2}" + \t{%2, %0|%0, %2} + v\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") - (set_attr "type" "ssemul") - (set_attr "prefix" "orig,vex") + (set_attr "type" "sse") + (set_attr "prefix" "orig,maybe_evex") + (set_attr "btver2_decode" "direct,double") (set_attr "mode" "")]) (define_expand "div3" @@ -1118,24 +1119,6 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) -(define_insn "_vmdiv3" - [(set (match_operand:VF_128 0 "register_operand" "=x,v") - (vec_merge:VF_128 - (div:VF_128 - (match_operand:VF_128 1 "register_operand" "0,v") - (match_operand:VF_128 2 "nonimmediate_operand" "xm,vm")) - (match_dup 1) - (const_int 1)))] - "TARGET_SSE" - "@ - div\t{%2, %0|%0, %2} - vdiv\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "noavx,avx") - (set_attr "type" "ssediv") - (set_attr "prefix" "orig,vex") - (set_attr "btver2_decode" "direct,double") - (set_attr "mode" "")]) - (define_insn "_rcp2" [(set (match_operand:VF1_128_256 0 "register_operand" "=x") (unspec:VF1_128_256