From patchwork Thu Sep 5 09:02:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Greenhalgh X-Patchwork-Id: 272833 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "www.sourceware.org", Issuer "StartCom Class 1 Primary Intermediate Server CA" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 51FF22C00AB for ; Thu, 5 Sep 2013 19:03:24 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=B8p75YKxBuTkLMTeH bnwe49/15P33MVXkqCZ+EVIli9Wdj1qSDNJz0oj8ar2FMgykU9LH81Xazzn+Zlor Vu/IfNnWNeiP2CbaEp/xOBGDBYqEr3C+0NE1O4RsDUkpGl433OvJoMo5zDqkoskq qOUIad46eLT8MBTR3lrcAMxXFA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=cTyOJxfoQgOQX+cL8ki/A8S svc0=; b=FeUCEmuz7ran3VR2dIBp7S1qr46Bd02P6+xweIK29tVzcL2pmhos7BA djx6u4Nmj/gq0LfyVXFl9Co1I1lAvgzRa7tB4wxIyzt/rrG1XQnQqD3vH9DvjAr3 7KNA5kS50KkESRUmqonZnj9fTZLlPN0v3rcQk/d5Ysy5eoerZjKk= Received: (qmail 5781 invoked by alias); 5 Sep 2013 09:03:09 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5768 invoked by uid 89); 5 Sep 2013 09:03:08 -0000 Received: from fw-tnat.cambridge.arm.com (HELO cam-smtp0.cambridge.arm.com) (217.140.96.21) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Thu, 05 Sep 2013 09:03:08 +0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.7 required=5.0 tests=AWL, BAYES_50, KAM_STOCKTIP, RP_MATCHES_RCVD, SPF_HELO_SOFTFAIL, SPF_SOFTFAIL autolearn=no version=3.3.2 X-HELO: cam-smtp0.cambridge.arm.com Received: from arm.com (e106375-lin.cambridge.arm.com [10.1.203.76]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id r8592o1T000928; Thu, 5 Sep 2013 10:02:50 +0100 Date: Thu, 5 Sep 2013 10:02:50 +0100 From: James Greenhalgh To: "gcc-patches@gcc.gnu.org" Cc: Marcus Shawcroft , Richard Earnshaw , Ramana Radhakrishnan Subject: Re: [AArch64, AArch32][Insn classification refactoring 6/N] Remove "neon_type" attribute Message-ID: <20130905090250.GA15984@arm.com> References: <1376916371-20476-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1376916371-20476-1-git-send-email-james.greenhalgh@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes *PING* Thanks, James On Mon, Aug 19, 2013 at 01:46:11PM +0100, James Greenhalgh wrote: > > Hi, > > This patch does two things: > > 1. Moves all the "neon_type" attribute values in the ARM backend into > "type", and removes "neon_type". > > 2. Splits type f_2_r and r_2_f to enable them to be used in a similar > way as neon_mcr et. al. > > The patch is principally a series of substitutions implementing the > above goal. I'm sorry that it is so long, but we touch every single > Neon pattern, and all neon-capable pipelines. > > Tested on aarch64-none-elf, bootstrapped on a chromebook, tested on > arm-none-eabi and sanity checked code output with no obvious regressions. > > Is this OK to go in to trunk? > > Thanks, > James > > ----- > 2013-08-19 James Greenhalgh > Sofiane Naci > > * config/aarch64/aarch64.md > (*movti_aarch64): Rename r_2_f and f_2_r. > (*movsf_aarch64): Likewise. > (*movdf_aarch64): Likewise. > (*movtf_aarch64): Likewise. > (aarch64_movdi_low): Likewise. > (aarch64_movdi_high): Likewise. > (aarch64_movhigh_di): Likewise. > (aarch64_movlow_di): Likewise. > (aarch64_movtilow_tilow): Likewise. > * config/arm/arm.c (cortexa7_older_only): Update for attribute change. > * config/arm/arm.md (attribute "neon_type"): Delete. Move attribute > values to config/arm/types.md > (attribute "conds"): Update for attribute change. > (anddi3_insn): Likewise. > (iordi3_insn): Likewise. > (xordi3_insn): Likewise. > (one_cmpldi2): Likewise. > * config/arm/arm1020e.md (v10_c2v): Update for attribute change. > (v10_v2c): Likewise. > * config/arm/cortex-a15-neon.md (cortex_a15_neon_int_1): Update for > attribute change. > (cortex_a15_neon_int_2): Likewise. > (cortex_a15_neon_int_3): Likewise. > (cortex_a15_neon_int_4): Likewise. > (cortex_a15_neon_int_5): Likewise. > (cortex_a15_neon_vqneg_vqabs): Likewise. > (cortex_a15_neon_vmov): Likewise. > (cortex_a15_neon_vaba): Likewise. > (cortex_a15_neon_vaba_qqq): Likewise. > (cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise. > (cortex_a15_neon_mul_qqq_8_16_32_ddd_32): Likewise. > (cortex_a15_neon_mul_qdd_64_32_long_qqd_16_ddd_32_\ > scalar_64_32_long_scalar): Likewise. > (cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise. > (cortex_a15_neon_mla_qqq_8_16): Likewise. > (cortex_a15_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\ > lotype_qdd_64_32_long): Likewise. > (cortex_a15_neon_mla_qqq_32_qqd_32_scalar): Likewise. > (cortex_a15_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise. > (cortex_a15_neon_mul_qqd_32_scalar): Likewise. > (cortex_a15_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise. > (cortex_a15_neon_shift_1): Likewise. > (cortex_a15_neon_shift_2): Likewise. > (cortex_a15_neon_shift_3): Likewise. > (cortex_a15_neon_vshl_ddd): Likewise. > (cortex_a15_neon_vqshl_vrshl_vqrshl_qqq): Likewise. > (cortex_a15_neon_vsra_vrsra): Likewise. > (cortex_a15_neon_fp_vadd_ddd_vabs_dd): Likewise. > (cortex_a15_neon_fp_vadd_qqq_vabs_qq): Likewise. > (cortex_a15_neon_fp_vmul_ddd): Likewise. > (cortex_a15_neon_fp_vmul_qqd): Likewise. > (cortex_a15_neon_fp_vmla_ddd): Likewise. > (cortex_a15_neon_fp_vmla_qqq): Likewise. > (cortex_a15_neon_fp_vmla_ddd_scalar): Likewise. > (cortex_a15_neon_fp_vmla_qqq_scalar): Likewise. > (cortex_a15_neon_fp_vrecps_vrsqrts_ddd): Likewise. > (cortex_a15_neon_fp_vrecps_vrsqrts_qqq): Likewise. > (cortex_a15_neon_bp_simple): Likewise. > (cortex_a15_neon_bp_2cycle): Likewise. > (cortex_a15_neon_bp_3cycle): Likewise. > (cortex_a15_neon_vld1_1_2_regs): Likewise. > (cortex_a15_neon_vld1_3_4_regs): Likewise. > (cortex_a15_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise. > (cortex_a15_neon_vld2_4_regs): Likewise. > (cortex_a15_neon_vld3_vld4): Likewise. > (cortex_a15_neon_vst1_1_2_regs_vst2_2_regs): Likewise. > (cortex_a15_neon_vst1_3_4_regs): Likewise. > (cortex_a15_neon_vst2_4_regs_vst3_vst4): Likewise. > (cortex_a15_neon_vst3_vst4): Likewise. > (cortex_a15_neon_vld1_vld2_lane): Likewise. > (cortex_a15_neon_vld3_vld4_lane" 10 > (cortex_a15_neon_vst1_vst2_lane): Likewise. > (cortex_a15_neon_vst3_vst4_lane): Likewise. > (cortex_a15_neon_vld3_vld4_all_lanes): Likewise. > (cortex_a15_neon_ldm_2): Likewise.0 > (cortex_a15_neon_stm_2): Likewise. > (cortex_a15_neon_mcr): Likewise. > (cortex_a15_neon_mcr_2_mcrr): Likewise. > (cortex_a15_neon_mrc): Likewise. > (cortex_a15_neon_mrrc): Likewise. > * config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute change. > (cortex_a15_alu_shift): Likewise. > (cortex_a15_alu_shift_reg): Likewise. > (cortex_a15_mult32): Likewise. > (cortex_a15_mult64): Likewise. > (cortex_a15_block): Likewise. > (cortex_a15_branch): Likewise. > (cortex_a15_load1): Likewise. > (cortex_a15_load3): Likewise. > (cortex_a15_store1): Likewise. > (cortex_a15_store3): Likewise. > (cortex_a15_call): Likewise. > * config/arm/cortex-a5.md (cortex_a5_r2f): Update for attribute change. > (cortex_a5_f2r): Likewise. > * config/arm/cortex-a53.md (cortex_a53_r2f): Update for attribute change. > (cortex_a53_f2r): Likewise. > * config/arm/cortex-a7.md > (cortex_a7_branch): Update for attribute change. > (cortex_a7_call): Likewise. > (cortex_a7_alu_imm): Likewise. > (cortex_a7_alu_reg): Likewise. > (cortex_a7_alu_shift): Likewise. > (cortex_a7_mul): Likewise. > (cortex_a7_load1): Likewise. > (cortex_a7_store1): Likewise. > (cortex_a7_load2): Likewise. > (cortex_a7_store2): Likewise. > (cortex_a7_load3): Likewise. > (cortex_a7_store3): Likewise. > (cortex_a7_load4): Likewise. > (cortex_a7_store4): Likewise. > (cortex_a7_fpalu): Likewise. > (cortex_a7_fconst): Likewise. > (cortex_a7_fpmuls): Likewise. > (cortex_a7_neon_mul): Likewise. > (cortex_a7_fpmacs): Likewise. > (cortex_a7_neon_mla: Likewise. > (cortex_a7_fpmuld: Likewise. > (cortex_a7_fpmacd: Likewise. > (cortex_a7_fpfmad: Likewise. > (cortex_a7_fdivs: Likewise. > (cortex_a7_fdivd: Likewise. > (cortex_a7_r2f: Likewise. > (cortex_a7_f2r: Likewise. > (cortex_a7_f_flags: Likewise. > (cortex_a7_f_loads: Likewise. > (cortex_a7_f_loadd: Likewise. > (cortex_a7_f_stores: Likewise. > (cortex_a7_f_stored: Likewise. > (cortex_a7_neon): Likewise. > * config/arm/cortex-a8-neon.md > (cortex_a8_neon_mrc): Update for attribute change. > (cortex_a8_neon_mrrc): Likewise. > (cortex_a8_neon_int_1): Likewise. > (cortex_a8_neon_int_2): Likewise. > (cortex_a8_neon_int_3): Likewise. > (cortex_a8_neon_int_4): Likewise. > (cortex_a8_neon_int_5): Likewise. > (cortex_a8_neon_vqneg_vqabs): Likewise. > (cortex_a8_neon_vmov): Likewise. > (cortex_a8_neon_vaba): Likewise. > (cortex_a8_neon_vaba_qqq): Likewise. > (cortex_a8_neon_vsma): Likewise. > (cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise. > (cortex_a8_neon_mul_qqq_8_16_32_ddd_32): Likewise. > (cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar): > Likewise. > (cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise. > (cortex_a8_neon_mla_qqq_8_16): Likewise. > (cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\ > long_scalar_qdd_64_32_long): Likewise. > (cortex_a8_neon_mla_qqq_32_qqd_32_scalar): Likewise. > (cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise. > (cortex_a8_neon_mul_qqd_32_scalar): Likewise. > (cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise. > (cortex_a8_neon_shift_1): Likewise. > (cortex_a8_neon_shift_2): Likewise. > (cortex_a8_neon_shift_3): Likewise. > (cortex_a8_neon_vshl_ddd): Likewise. > (cortex_a8_neon_vqshl_vrshl_vqrshl_qqq): Likewise. > (cortex_a8_neon_vsra_vrsra): Likewise. > (cortex_a8_neon_fp_vadd_ddd_vabs_dd): Likewise. > (cortex_a8_neon_fp_vadd_qqq_vabs_qq): Likewise. > (cortex_a8_neon_fp_vsum): Likewise. > (cortex_a8_neon_fp_vmul_ddd): Likewise. > (cortex_a8_neon_fp_vmul_qqd): Likewise. > (cortex_a8_neon_fp_vmla_ddd): Likewise. > (cortex_a8_neon_fp_vmla_qqq): Likewise. > (cortex_a8_neon_fp_vmla_ddd_scalar): Likewise. > (cortex_a8_neon_fp_vmla_qqq_scalar): Likewise. > (cortex_a8_neon_fp_vrecps_vrsqrts_ddd): Likewise. > (cortex_a8_neon_fp_vrecps_vrsqrts_qqq): Likewise. > (cortex_a8_neon_bp_simple): Likewise. > (cortex_a8_neon_bp_2cycle): Likewise. > (cortex_a8_neon_bp_3cycle): Likewise. > (cortex_a8_neon_ldr): Likewise. > (cortex_a8_neon_str): Likewise. > (cortex_a8_neon_vld1_1_2_regs): Likewise. > (cortex_a8_neon_vld1_3_4_regs): Likewise. > (cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise. > (cortex_a8_neon_vld2_4_regs): Likewise. > (cortex_a8_neon_vld3_vld4): Likewise. > (cortex_a8_neon_vst1_1_2_regs_vst2_2_regs): Likewise. > (cortex_a8_neon_vst1_3_4_regs): Likewise. > (cortex_a8_neon_vst2_4_regs_vst3_vst4): Likewise. > (cortex_a8_neon_vst3_vst4): Likewise. > (cortex_a8_neon_vld1_vld2_lane): Likewise. > (cortex_a8_neon_vld3_vld4_lane): Likewise. > (cortex_a8_neon_vst1_vst2_lane): Likewise. > (cortex_a8_neon_vst3_vst4_lane): Likewise. > (cortex_a8_neon_vld3_vld4_all_lanes): Likewise. > (cortex_a8_neon_mcr): Likewise. > (cortex_a8_neon_mcr_2_mcrr): Likewise. > * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change. > * config/arm/cortex-a9-neon.md (ca9_neon_mrc): Update for attribute change. > (ca9_neon_mrrc): Likewise. > (cortex_a9_neon_int_1): Likewise. > (cortex_a9_neon_int_2): Likewise. > (cortex_a9_neon_int_3): Likewise. > (cortex_a9_neon_int_4): Likewise. > (cortex_a9_neon_int_5): Likewise. > (cortex_a9_neon_vqneg_vqabs): Likewise. > (cortex_a9_neon_vmov): Likewise. > (cortex_a9_neon_vaba): Likewise. > (cortex_a9_neon_vaba_qqq): Likewise. > (cortex_a9_neon_vsma): Likewise. > (cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise. > (cortex_a9_neon_mul_qqq_8_16_32_ddd_32): Likewise. > (cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar): > Likewise. > (cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise. > (cortex_a9_neon_mla_qqq_8_16): Likewise. > (cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\ > long_scalar_qdd_64_32_long): Likewise. > (cortex_a9_neon_mla_qqq_32_qqd_32_scalar): Likewise. > (cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise. > (cortex_a9_neon_mul_qqd_32_scalar): Likewise. > (cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise. > (cortex_a9_neon_shift_1): Likewise. > (cortex_a9_neon_shift_2): Likewise. > (cortex_a9_neon_shift_3): Likewise. > (cortex_a9_neon_vshl_ddd): Likewise. > (cortex_a9_neon_vqshl_vrshl_vqrshl_qqq): Likewise. > (cortex_a9_neon_vsra_vrsra): Likewise. > (cortex_a9_neon_fp_vadd_ddd_vabs_dd): Likewise. > (cortex_a9_neon_fp_vadd_qqq_vabs_qq): Likewise. > (cortex_a9_neon_fp_vsum): Likewise. > (cortex_a9_neon_fp_vmul_ddd): Likewise. > (cortex_a9_neon_fp_vmul_qqd): Likewise. > (cortex_a9_neon_fp_vmla_ddd): Likewise. > (cortex_a9_neon_fp_vmla_qqq): Likewise. > (cortex_a9_neon_fp_vmla_ddd_scalar): Likewise. > (cortex_a9_neon_fp_vmla_qqq_scalar): Likewise. > (cortex_a9_neon_fp_vrecps_vrsqrts_ddd): Likewise. > (cortex_a9_neon_fp_vrecps_vrsqrts_qqq): Likewise. > (cortex_a9_neon_bp_simple): Likewise. > (cortex_a9_neon_bp_2cycle): Likewise. > (cortex_a9_neon_bp_3cycle): Likewise. > (cortex_a9_neon_ldr): Likewise. > (cortex_a9_neon_str): Likewise. > (cortex_a9_neon_vld1_1_2_regs): Likewise. > (cortex_a9_neon_vld1_3_4_regs): Likewise. > (cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise. > (cortex_a9_neon_vld2_4_regs): Likewise. > (cortex_a9_neon_vld3_vld4): Likewise. > (cortex_a9_neon_vst1_1_2_regs_vst2_2_regs): Likewise. > (cortex_a9_neon_vst1_3_4_regs): Likewise. > (cortex_a9_neon_vst2_4_regs_vst3_vst4): Likewise. > (cortex_a9_neon_vst3_vst4): Likewise. > (cortex_a9_neon_vld1_vld2_lane): Likewise. > (cortex_a9_neon_vld3_vld4_lane): Likewise. > (cortex_a9_neon_vst1_vst2_lane): Likewise. > (cortex_a9_neon_vst3_vst4_lane): Likewise. > (cortex_a9_neon_vld3_vld4_all_lanes): Likewise. > (cortex_a9_neon_mcr): Likewise. > (cortex_a9_neon_mcr_2_mcrr): Likewise. > * config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute change. > (cortex_a9_fps): Likewise. > * config/arm/cortex-m4-fpu.md (cortex_m4_vmov_2): Update for attribute > change. > (cortex_m4_fmuls): Likewise. > * config/arm/cortex-r4f.md (cortex_r4_mcr): Update for attribute change. > (cortex_r4_mrc): Likewise. > * config/arm/iterators.md: Update comment referring to neon_type. > * config/arm/iwmmxt.md > (iwmmxt_arm_movdi): Update for attribute change. > (iwmmxt_movsi_insn): Likewise. > * config/arm/marvell-pj4.md > (pj4_vfp_to_core): Update for attribute change. > (pj4_core_to_vfp): Likewise. > * config/arm/neon-schedgen.ml (emit_insn_reservations): Update for > attribute change. > * config/arm/neon.md (neon_mov): Update for attribute changes. > (movmisalign_neon_store): Likewise. > (movmisalign_neon_load): Likewise. > (vec_set_internal): Likewise. > (vec_setv2di_internal): Likewise. > (vec_extract): Likewise. > (vec_extractv2di): Likewise. > (add3_neon): Likewise. > (adddi3_neon): Likewise. > (sub3_neon): Likewise. > (subdi3_neon): Likewise. > (mul3_neon): Likewise. > (mul3add_neon): Likewise. > (mul3negadd_neon): Likewise. > (fma4)): Likewise. > (fma4_intrinsic): Likewise. > (fmsub4)): Likewise. > (fmsub4_intrinsic): Likewise. > (neon_vrint): Likewise. > (ior3): Likewise. > (and3): Likewise. > (anddi3_neon): Likewise. > (orn3_neon): Likewise. > (orndi3_neon): Likewise. > (bic3_neon): Likewise. > (bicdi3_neon): Likewise. > (xor3): Likewise. > (one_cmpl2): Likewise. > (abs2): Likewise. > (neg2): Likewise. > (umin3_neon): Likewise. > (umax3_neon): Likewise. > (smin3_neon): Likewise. > (smax3_neon): Likewise. > (vashl3): Likewise. > (vashr3_imm): Likewise. > (vlshr3_imm): Likewise. > (ashl3_signed): Likewise. > (ashl3_unsigned): Likewise. > (neon_load_count): Likewise. > (ashldi3_neon_noclobber): Likewise. > (signed_shift_di3_neon): Likewise. > (unsigned_shift_di3_neon): Likewise. > (ashrdi3_neon_imm_noclobber): Likewise. > (lshrdi3_neon_imm_noclobber): Likewise. > (widen_ssum3): Likewise. > (widen_usum3): Likewise. > (quad_halves_v4si): Likewise. > (quad_halves_v4sf): Likewise. > (quad_halves_v8hi): Likewise. > (quad_halves_v16qi): Likewise. > (reduc_splus_v2di): Likewise. > (neon_vpadd_internal): Likewise. > (neon_vpsmin): Likewise. > (neon_vpsmax): Likewise. > (neon_vpumin): Likewise. > (neon_vpumax): Likewise. > (ss_add_neon): Likewise. > (us_add_neon): Likewise. > (ss_sub_neon): Likewise. > (us_sub_neon): Likewise. > (neon_vadd_unspec): Likewise. > (neon_vaddl): Likewise. > (neon_vaddw): Likewise. > (neon_vhadd): Likewise. > (neon_vqadd): Likewise. > (neon_vaddhn): Likewise. > (neon_vmul): Likewise. > (neon_vmla): Likewise. > (neon_vmlal): Likewise. > (neon_vmls): Likewise. > (neon_vmlsl): Likewise. > (neon_vqdmulh): Likewise. > (neon_vqdmlal): Likewise. > (neon_vqdmlsl): Likewise. > (neon_vmull): Likewise. > (neon_vqdmull): Likewise. > (neon_vsub_unspec): Likewise. > (neon_vsubl): Likewise. > (neon_vsubw): Likewise. > (neon_vqsub): Likewise. > (neon_vhsub): Likewise. > (neon_vsubhn): Likewise. > (neon_vceq): Likewise. > (neon_vcge): Likewise. > (neon_vcgeu): Likewise. > (neon_vcgt): Likewise. > (neon_vcgtu): Likewise. > (neon_vcle): Likewise. > (neon_vclt): Likewise. > (neon_vcage): Likewise. > (neon_vcagt): Likewise. > (neon_vtst): Likewise. > (neon_vabd): Likewise. > (neon_vabdl): Likewise. > (neon_vaba): Likewise. > (neon_vabal): Likewise. > (neon_vmax): Likewise. > (neon_vmin): Likewise. > (neon_vpaddl): Likewise. > (neon_vpadal): Likewise. > (neon_vpmax): Likewise. > (neon_vpmin): Likewise. > (neon_vrecps): Likewise. > (neon_vrsqrts): Likewise. > (neon_vqabs): Likewise. > (neon_vqneg): Likewise. > (neon_vcls): Likewise. > (clz2): Likewise. > (popcount2): Likewise. > (neon_vrecpe): Likewise. > (neon_vrsqrte): Likewise. > (neon_vget_lane_sext_internal): Likewise. > (neon_vget_lane_zext_internal): Likewise. > (neon_vdup_n): Likewise. > (neon_vdup_nv2di): Likewise. > (neon_vdpu_lane_internal): Likewise. > (neon_vswp): Likewise. > (float2): Likewise. > (floatuns2): Likewise. > (fix_trunc)2): Likewise > (fixuns_trunc (neon_vcvt): Likewise. > (neon_vcvtv4sfv4hf): Likewise. > (neon_vcvtv4hfv4sf): Likewise. > (neon_vcvt_n): Likewise. > (neon_vmovn): Likewise. > (neon_vqmovn): Likewise. > (neon_vqmovun): Likewise. > (neon_vmovl): Likewise. > (neon_vmul_lane): Likewise. > (neon_vmull_lane): Likewise. > (neon_vqdmull_lane): Likewise. > (neon_vqdmulh_lane): Likewise. > (neon_vmla_lane): Likewise. > (neon_vmlal_lane): Likewise. > (neon_vqdmlal_lane): Likewise. > (neon_vmls_lane): Likewise. > (neon_vmlsl_lane): Likewise. > (neon_vqdmlsl_lane): Likewise. > (neon_vext): Likewise. > (neon_vrev64): Likewise. > (neon_vrev32): Likewise. > (neon_vrev16): Likewise. > (neon_vbsl_internal): Likewise. > (neon_vshl): Likewise. > (neon_vqshl): Likewise. > (neon_vshr_n): Likewise. > (neon_vshrn_n): Likewise. > (neon_vqshrn_n): Likewise. > (neon_vqshrun_n): Likewise. > (neon_vshl_n): Likewise. > (neon_vqshl_n): Likewise. > (neon_vqshlu_n): Likewise. > (neon_vshll_n): Likewise. > (neon_vsra_n): Likewise. > (neon_vsri_n): Likewise. > (neon_vsli_n): Likewise. > (neon_vtbl1v8qi): Likewise. > (neon_vtbl2v8qi): Likewise. > (neon_vtbl3v8qi): Likewise. > (neon_vtbl4v8qi): Likewise. > (neon_vtbx1v8qi): Likewise. > (neon_vtbx2v8qi): Likewise. > (neon_vtbx3v8qi): Likewise. > (neon_vtbx4v8qi): Likewise. > (neon_vtrn_internal): Likewise. > (neon_vzip_internal): Likewise. > (neon_vuzp_internal): Likewise. > (neon_vld1): Likewise. > (neon_vld1_lane): Likewise. > (neon_vld1_dup): Likewise. > (neon_vld1_dupv2di): Likewise. > (neon_vst1): Likewise. > (neon_vst1_lane): Likewise. > (neon_vld2): Likewise. > (neon_vld2_lane): Likewise. > (neon_vld2_dup): Likewise. > (neon_vst2): Likewise. > (neon_vst2_lane): Likewise. > (neon_vld3): Likewise. > (neon_vld3qa): Likewise. > (neon_vld3qb): Likewise. > (neon_vld3_lane): Likewise. > (neon_vld3_dup): Likewise. > (neon_vst3): Likewise. > (neon_vst3qa): Likewise. > (neon_vst3qb): Likewise. > (neon_vst3_lane): Likewise. > (neon_vld4): Likewise. > (neon_vld4qa): Likewise. > (neon_vld4qb): Likewise. > (neon_vld4_lane): Likewise. > (neon_vld4_dup): Likewise. > (neon_vst4): Likewise. > (neon_vst4qa): Likewise. > (neon_vst4qb): Likewise. > (neon_vst4_lane): Likewise. > (neon_vec_unpack_lo_): Likewise. > (neon_vec_unpack_hi_): Likewise. > (neon_vec_mult_lo_): Likewise. > (neon_vec_mult_hi_): Likewise. > (neon_vec_shiftl_): Likewise. > (neon_unpack_): Likewise. > (neon_vec_mult_): Likewise. > (vec_pack_trunc_): Likewise. > (neon_vec_pack_trunk_): Likewise. > (neon_vabd_2): Likewise. > (neon_vabd_3): Likewise. > * config/arm/types.md (type): Add Neon types. > * config/arm/vfp.md (arm_movsi_vfp): Update for attribute changes. > (thumb2_movsi_vfp): Likewise. > (movdi_vfp): Likewise. > (movdi_vfp_cortexa8): Likewise. > (movhf_vfp_neon): Likewise. > (movhf_vfp): Likewiwse. > (movsf_vfp): Likewiwse. > (thumb2_movsf_vfp): Likewiwse. > (movdf_vfp): Likewise. > (thumb2_movdf_vfp): Likewise. > (movsfcc_vfp): Likewise. > (thumb2_movsfcc_vfp): Likewise. > (movdfcc_vfp): Likewise. > (thumb2_movdfcc_vfp): Likewise. > * config/arm/vfp11.md (vfp_fload): Update for attribute change. > (vfp_fstore): Likewise. > * doc/md.texi: Change references to neon_type to refer to type. > From 13aed57e3fe9e9b6f405a01544540526d340b2d3 Mon Sep 17 00:00:00 2001 From: James Greenhalgh Date: Fri, 9 Aug 2013 16:34:56 +0100 Subject: [AArch64, AArch32][Insn classification refactoring 6/N] Remove "neon_type" attribute MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------1.8.3-rc0" This is a multi-part message in MIME format. --------------1.8.3-rc0 Content-Type: text/plain; charset=UTF-8; format=fixed Content-Transfer-Encoding: 8bit Hi, This patch does two things: 1. Moves all the "neon_type" attribute values in the ARM backend into "type", and removes "neon_type". 2. Splits type f_2_r and r_2_f to enable them to be used in a similar way as neon_mcr et. al. The patch is principally a series of substitutions implementing the above goals. I'm sorry that it is so long, but we touch every single Neon pattern, and all neon-capable pipelines. Tested on aarch64-none-elf, bootstrapped on a chromebook, tested on arm-none-eabi and sanity checked code output with no obvious regressions. Is this OK? Thanks, James ----- 2013-08-19 James Greenhalgh Sofiane Naci * config/aarch64/aarch64.md (*movti_aarch64): Rename r_2_f and f_2_r. (*movsf_aarch64): Likewise. (*movdf_aarch64): Likewise. (*movtf_aarch64): Likewise. (aarch64_movdi_low): Likewise. (aarch64_movdi_high): Likewise. (aarch64_movhigh_di): Likewise. (aarch64_movlow_di): Likewise. (aarch64_movtilow_tilow): Likewise. * config/arm/arm.c (cortexa7_older_only): Update for attribute change. * config/arm/arm.md (attribute "neon_type"): Delete. Move attribute values to config/arm/types.md (attribute "conds"): Update for attribute change. (anddi3_insn): Likewise. (iordi3_insn): Likewise. (xordi3_insn): Likewise. (one_cmpldi2): Likewise. * config/arm/arm1020e.md (v10_c2v): Update for attribute change. (v10_v2c): Likewise. * config/arm/cortex-a15-neon.md (cortex_a15_neon_int_1): Update for attribute change. (cortex_a15_neon_int_2): Likewise. (cortex_a15_neon_int_3): Likewise. (cortex_a15_neon_int_4): Likewise. (cortex_a15_neon_int_5): Likewise. (cortex_a15_neon_vqneg_vqabs): Likewise. (cortex_a15_neon_vmov): Likewise. (cortex_a15_neon_vaba): Likewise. (cortex_a15_neon_vaba_qqq): Likewise. (cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise. (cortex_a15_neon_mul_qqq_8_16_32_ddd_32): Likewise. (cortex_a15_neon_mul_qdd_64_32_long_qqd_16_ddd_32_\ scalar_64_32_long_scalar): Likewise. (cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise. (cortex_a15_neon_mla_qqq_8_16): Likewise. (cortex_a15_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\ lotype_qdd_64_32_long): Likewise. (cortex_a15_neon_mla_qqq_32_qqd_32_scalar): Likewise. (cortex_a15_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise. (cortex_a15_neon_mul_qqd_32_scalar): Likewise. (cortex_a15_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise. (cortex_a15_neon_shift_1): Likewise. (cortex_a15_neon_shift_2): Likewise. (cortex_a15_neon_shift_3): Likewise. (cortex_a15_neon_vshl_ddd): Likewise. (cortex_a15_neon_vqshl_vrshl_vqrshl_qqq): Likewise. (cortex_a15_neon_vsra_vrsra): Likewise. (cortex_a15_neon_fp_vadd_ddd_vabs_dd): Likewise. (cortex_a15_neon_fp_vadd_qqq_vabs_qq): Likewise. (cortex_a15_neon_fp_vmul_ddd): Likewise. (cortex_a15_neon_fp_vmul_qqd): Likewise. (cortex_a15_neon_fp_vmla_ddd): Likewise. (cortex_a15_neon_fp_vmla_qqq): Likewise. (cortex_a15_neon_fp_vmla_ddd_scalar): Likewise. (cortex_a15_neon_fp_vmla_qqq_scalar): Likewise. (cortex_a15_neon_fp_vrecps_vrsqrts_ddd): Likewise. (cortex_a15_neon_fp_vrecps_vrsqrts_qqq): Likewise. (cortex_a15_neon_bp_simple): Likewise. (cortex_a15_neon_bp_2cycle): Likewise. (cortex_a15_neon_bp_3cycle): Likewise. (cortex_a15_neon_vld1_1_2_regs): Likewise. (cortex_a15_neon_vld1_3_4_regs): Likewise. (cortex_a15_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise. (cortex_a15_neon_vld2_4_regs): Likewise. (cortex_a15_neon_vld3_vld4): Likewise. (cortex_a15_neon_vst1_1_2_regs_vst2_2_regs): Likewise. (cortex_a15_neon_vst1_3_4_regs): Likewise. (cortex_a15_neon_vst2_4_regs_vst3_vst4): Likewise. (cortex_a15_neon_vst3_vst4): Likewise. (cortex_a15_neon_vld1_vld2_lane): Likewise. (cortex_a15_neon_vld3_vld4_lane" 10 (cortex_a15_neon_vst1_vst2_lane): Likewise. (cortex_a15_neon_vst3_vst4_lane): Likewise. (cortex_a15_neon_vld3_vld4_all_lanes): Likewise. (cortex_a15_neon_ldm_2): Likewise.0 (cortex_a15_neon_stm_2): Likewise. (cortex_a15_neon_mcr): Likewise. (cortex_a15_neon_mcr_2_mcrr): Likewise. (cortex_a15_neon_mrc): Likewise. (cortex_a15_neon_mrrc): Likewise. * config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute change. (cortex_a15_alu_shift): Likewise. (cortex_a15_alu_shift_reg): Likewise. (cortex_a15_mult32): Likewise. (cortex_a15_mult64): Likewise. (cortex_a15_block): Likewise. (cortex_a15_branch): Likewise. (cortex_a15_load1): Likewise. (cortex_a15_load3): Likewise. (cortex_a15_store1): Likewise. (cortex_a15_store3): Likewise. (cortex_a15_call): Likewise. * config/arm/cortex-a5.md (cortex_a5_r2f): Update for attribute change. (cortex_a5_f2r): Likewise. * config/arm/cortex-a53.md (cortex_a53_r2f): Update for attribute change. (cortex_a53_f2r): Likewise. * config/arm/cortex-a7.md (cortex_a7_branch): Update for attribute change. (cortex_a7_call): Likewise. (cortex_a7_alu_imm): Likewise. (cortex_a7_alu_reg): Likewise. (cortex_a7_alu_shift): Likewise. (cortex_a7_mul): Likewise. (cortex_a7_load1): Likewise. (cortex_a7_store1): Likewise. (cortex_a7_load2): Likewise. (cortex_a7_store2): Likewise. (cortex_a7_load3): Likewise. (cortex_a7_store3): Likewise. (cortex_a7_load4): Likewise. (cortex_a7_store4): Likewise. (cortex_a7_fpalu): Likewise. (cortex_a7_fconst): Likewise. (cortex_a7_fpmuls): Likewise. (cortex_a7_neon_mul): Likewise. (cortex_a7_fpmacs): Likewise. (cortex_a7_neon_mla: Likewise. (cortex_a7_fpmuld: Likewise. (cortex_a7_fpmacd: Likewise. (cortex_a7_fpfmad: Likewise. (cortex_a7_fdivs: Likewise. (cortex_a7_fdivd: Likewise. (cortex_a7_r2f: Likewise. (cortex_a7_f2r: Likewise. (cortex_a7_f_flags: Likewise. (cortex_a7_f_loads: Likewise. (cortex_a7_f_loadd: Likewise. (cortex_a7_f_stores: Likewise. (cortex_a7_f_stored: Likewise. (cortex_a7_neon): Likewise. * config/arm/cortex-a8-neon.md (cortex_a8_neon_mrc): Update for attribute change. (cortex_a8_neon_mrrc): Likewise. (cortex_a8_neon_int_1): Likewise. (cortex_a8_neon_int_2): Likewise. (cortex_a8_neon_int_3): Likewise. (cortex_a8_neon_int_4): Likewise. (cortex_a8_neon_int_5): Likewise. (cortex_a8_neon_vqneg_vqabs): Likewise. (cortex_a8_neon_vmov): Likewise. (cortex_a8_neon_vaba): Likewise. (cortex_a8_neon_vaba_qqq): Likewise. (cortex_a8_neon_vsma): Likewise. (cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise. (cortex_a8_neon_mul_qqq_8_16_32_ddd_32): Likewise. (cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar): Likewise. (cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise. (cortex_a8_neon_mla_qqq_8_16): Likewise. (cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\ long_scalar_qdd_64_32_long): Likewise. (cortex_a8_neon_mla_qqq_32_qqd_32_scalar): Likewise. (cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise. (cortex_a8_neon_mul_qqd_32_scalar): Likewise. (cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise. (cortex_a8_neon_shift_1): Likewise. (cortex_a8_neon_shift_2): Likewise. (cortex_a8_neon_shift_3): Likewise. (cortex_a8_neon_vshl_ddd): Likewise. (cortex_a8_neon_vqshl_vrshl_vqrshl_qqq): Likewise. (cortex_a8_neon_vsra_vrsra): Likewise. (cortex_a8_neon_fp_vadd_ddd_vabs_dd): Likewise. (cortex_a8_neon_fp_vadd_qqq_vabs_qq): Likewise. (cortex_a8_neon_fp_vsum): Likewise. (cortex_a8_neon_fp_vmul_ddd): Likewise. (cortex_a8_neon_fp_vmul_qqd): Likewise. (cortex_a8_neon_fp_vmla_ddd): Likewise. (cortex_a8_neon_fp_vmla_qqq): Likewise. (cortex_a8_neon_fp_vmla_ddd_scalar): Likewise. (cortex_a8_neon_fp_vmla_qqq_scalar): Likewise. (cortex_a8_neon_fp_vrecps_vrsqrts_ddd): Likewise. (cortex_a8_neon_fp_vrecps_vrsqrts_qqq): Likewise. (cortex_a8_neon_bp_simple): Likewise. (cortex_a8_neon_bp_2cycle): Likewise. (cortex_a8_neon_bp_3cycle): Likewise. (cortex_a8_neon_ldr): Likewise. (cortex_a8_neon_str): Likewise. (cortex_a8_neon_vld1_1_2_regs): Likewise. (cortex_a8_neon_vld1_3_4_regs): Likewise. (cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise. (cortex_a8_neon_vld2_4_regs): Likewise. (cortex_a8_neon_vld3_vld4): Likewise. (cortex_a8_neon_vst1_1_2_regs_vst2_2_regs): Likewise. (cortex_a8_neon_vst1_3_4_regs): Likewise. (cortex_a8_neon_vst2_4_regs_vst3_vst4): Likewise. (cortex_a8_neon_vst3_vst4): Likewise. (cortex_a8_neon_vld1_vld2_lane): Likewise. (cortex_a8_neon_vld3_vld4_lane): Likewise. (cortex_a8_neon_vst1_vst2_lane): Likewise. (cortex_a8_neon_vst3_vst4_lane): Likewise. (cortex_a8_neon_vld3_vld4_all_lanes): Likewise. (cortex_a8_neon_mcr): Likewise. (cortex_a8_neon_mcr_2_mcrr): Likewise. * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change. * config/arm/cortex-a9-neon.md (ca9_neon_mrc): Update for attribute change. (ca9_neon_mrrc): Likewise. (cortex_a9_neon_int_1): Likewise. (cortex_a9_neon_int_2): Likewise. (cortex_a9_neon_int_3): Likewise. (cortex_a9_neon_int_4): Likewise. (cortex_a9_neon_int_5): Likewise. (cortex_a9_neon_vqneg_vqabs): Likewise. (cortex_a9_neon_vmov): Likewise. (cortex_a9_neon_vaba): Likewise. (cortex_a9_neon_vaba_qqq): Likewise. (cortex_a9_neon_vsma): Likewise. (cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long): Likewise. (cortex_a9_neon_mul_qqq_8_16_32_ddd_32): Likewise. (cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar): Likewise. (cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long): Likewise. (cortex_a9_neon_mla_qqq_8_16): Likewise. (cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_\ long_scalar_qdd_64_32_long): Likewise. (cortex_a9_neon_mla_qqq_32_qqd_32_scalar): Likewise. (cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar): Likewise. (cortex_a9_neon_mul_qqd_32_scalar): Likewise. (cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar): Likewise. (cortex_a9_neon_shift_1): Likewise. (cortex_a9_neon_shift_2): Likewise. (cortex_a9_neon_shift_3): Likewise. (cortex_a9_neon_vshl_ddd): Likewise. (cortex_a9_neon_vqshl_vrshl_vqrshl_qqq): Likewise. (cortex_a9_neon_vsra_vrsra): Likewise. (cortex_a9_neon_fp_vadd_ddd_vabs_dd): Likewise. (cortex_a9_neon_fp_vadd_qqq_vabs_qq): Likewise. (cortex_a9_neon_fp_vsum): Likewise. (cortex_a9_neon_fp_vmul_ddd): Likewise. (cortex_a9_neon_fp_vmul_qqd): Likewise. (cortex_a9_neon_fp_vmla_ddd): Likewise. (cortex_a9_neon_fp_vmla_qqq): Likewise. (cortex_a9_neon_fp_vmla_ddd_scalar): Likewise. (cortex_a9_neon_fp_vmla_qqq_scalar): Likewise. (cortex_a9_neon_fp_vrecps_vrsqrts_ddd): Likewise. (cortex_a9_neon_fp_vrecps_vrsqrts_qqq): Likewise. (cortex_a9_neon_bp_simple): Likewise. (cortex_a9_neon_bp_2cycle): Likewise. (cortex_a9_neon_bp_3cycle): Likewise. (cortex_a9_neon_ldr): Likewise. (cortex_a9_neon_str): Likewise. (cortex_a9_neon_vld1_1_2_regs): Likewise. (cortex_a9_neon_vld1_3_4_regs): Likewise. (cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes): Likewise. (cortex_a9_neon_vld2_4_regs): Likewise. (cortex_a9_neon_vld3_vld4): Likewise. (cortex_a9_neon_vst1_1_2_regs_vst2_2_regs): Likewise. (cortex_a9_neon_vst1_3_4_regs): Likewise. (cortex_a9_neon_vst2_4_regs_vst3_vst4): Likewise. (cortex_a9_neon_vst3_vst4): Likewise. (cortex_a9_neon_vld1_vld2_lane): Likewise. (cortex_a9_neon_vld3_vld4_lane): Likewise. (cortex_a9_neon_vst1_vst2_lane): Likewise. (cortex_a9_neon_vst3_vst4_lane): Likewise. (cortex_a9_neon_vld3_vld4_all_lanes): Likewise. (cortex_a9_neon_mcr): Likewise. (cortex_a9_neon_mcr_2_mcrr): Likewise. * config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute change. (cortex_a9_fps): Likewise. * config/arm/cortex-m4-fpu.md (cortex_m4_vmov_2): Update for attribute change. (cortex_m4_fmuls): Likewise. * config/arm/cortex-r4f.md (cortex_r4_mcr): Update for attribute change. (cortex_r4_mrc): Likewise. * config/arm/iterators.md: Update comment referring to neon_type. * config/arm/iwmmxt.md (iwmmxt_arm_movdi): Update for attribute change. (iwmmxt_movsi_insn): Likewise. * config/arm/marvell-pj4.md (pj4_vfp_to_core): Update for attribute change. (pj4_core_to_vfp): Likewise. * config/arm/neon-schedgen.ml (emit_insn_reservations): Update for attribute change. * config/arm/neon.md (neon_mov): Update for attribute changes. (movmisalign_neon_store): Likewise. (movmisalign_neon_load): Likewise. (vec_set_internal): Likewise. (vec_setv2di_internal): Likewise. (vec_extract): Likewise. (vec_extractv2di): Likewise. (add3_neon): Likewise. (adddi3_neon): Likewise. (sub3_neon): Likewise. (subdi3_neon): Likewise. (mul3_neon): Likewise. (mul3add_neon): Likewise. (mul3negadd_neon): Likewise. (fma4)): Likewise. (fma4_intrinsic): Likewise. (fmsub4)): Likewise. (fmsub4_intrinsic): Likewise. (neon_vrint): Likewise. (ior3): Likewise. (and3): Likewise. (anddi3_neon): Likewise. (orn3_neon): Likewise. (orndi3_neon): Likewise. (bic3_neon): Likewise. (bicdi3_neon): Likewise. (xor3): Likewise. (one_cmpl2): Likewise. (abs2): Likewise. (neg2): Likewise. (umin3_neon): Likewise. (umax3_neon): Likewise. (smin3_neon): Likewise. (smax3_neon): Likewise. (vashl3): Likewise. (vashr3_imm): Likewise. (vlshr3_imm): Likewise. (ashl3_signed): Likewise. (ashl3_unsigned): Likewise. (neon_load_count): Likewise. (ashldi3_neon_noclobber): Likewise. (signed_shift_di3_neon): Likewise. (unsigned_shift_di3_neon): Likewise. (ashrdi3_neon_imm_noclobber): Likewise. (lshrdi3_neon_imm_noclobber): Likewise. (widen_ssum3): Likewise. (widen_usum3): Likewise. (quad_halves_v4si): Likewise. (quad_halves_v4sf): Likewise. (quad_halves_v8hi): Likewise. (quad_halves_v16qi): Likewise. (reduc_splus_v2di): Likewise. (neon_vpadd_internal): Likewise. (neon_vpsmin): Likewise. (neon_vpsmax): Likewise. (neon_vpumin): Likewise. (neon_vpumax): Likewise. (ss_add_neon): Likewise. (us_add_neon): Likewise. (ss_sub_neon): Likewise. (us_sub_neon): Likewise. (neon_vadd_unspec): Likewise. (neon_vaddl): Likewise. (neon_vaddw): Likewise. (neon_vhadd): Likewise. (neon_vqadd): Likewise. (neon_vaddhn): Likewise. (neon_vmul): Likewise. (neon_vmla): Likewise. (neon_vmlal): Likewise. (neon_vmls): Likewise. (neon_vmlsl): Likewise. (neon_vqdmulh): Likewise. (neon_vqdmlal): Likewise. (neon_vqdmlsl): Likewise. (neon_vmull): Likewise. (neon_vqdmull): Likewise. (neon_vsub_unspec): Likewise. (neon_vsubl): Likewise. (neon_vsubw): Likewise. (neon_vqsub): Likewise. (neon_vhsub): Likewise. (neon_vsubhn): Likewise. (neon_vceq): Likewise. (neon_vcge): Likewise. (neon_vcgeu): Likewise. (neon_vcgt): Likewise. (neon_vcgtu): Likewise. (neon_vcle): Likewise. (neon_vclt): Likewise. (neon_vcage): Likewise. (neon_vcagt): Likewise. (neon_vtst): Likewise. (neon_vabd): Likewise. (neon_vabdl): Likewise. (neon_vaba): Likewise. (neon_vabal): Likewise. (neon_vmax): Likewise. (neon_vmin): Likewise. (neon_vpaddl): Likewise. (neon_vpadal): Likewise. (neon_vpmax): Likewise. (neon_vpmin): Likewise. (neon_vrecps): Likewise. (neon_vrsqrts): Likewise. (neon_vqabs): Likewise. (neon_vqneg): Likewise. (neon_vcls): Likewise. (clz2): Likewise. (popcount2): Likewise. (neon_vrecpe): Likewise. (neon_vrsqrte): Likewise. (neon_vget_lane_sext_internal): Likewise. (neon_vget_lane_zext_internal): Likewise. (neon_vdup_n): Likewise. (neon_vdup_nv2di): Likewise. (neon_vdpu_lane_internal): Likewise. (neon_vswp): Likewise. (float2): Likewise. (floatuns2): Likewise. (fix_trunc)2): Likewise (fixuns_trunc): Likewise. (neon_vcvtv4sfv4hf): Likewise. (neon_vcvtv4hfv4sf): Likewise. (neon_vcvt_n): Likewise. (neon_vmovn): Likewise. (neon_vqmovn): Likewise. (neon_vqmovun): Likewise. (neon_vmovl): Likewise. (neon_vmul_lane): Likewise. (neon_vmull_lane): Likewise. (neon_vqdmull_lane): Likewise. (neon_vqdmulh_lane): Likewise. (neon_vmla_lane): Likewise. (neon_vmlal_lane): Likewise. (neon_vqdmlal_lane): Likewise. (neon_vmls_lane): Likewise. (neon_vmlsl_lane): Likewise. (neon_vqdmlsl_lane): Likewise. (neon_vext): Likewise. (neon_vrev64): Likewise. (neon_vrev32): Likewise. (neon_vrev16): Likewise. (neon_vbsl_internal): Likewise. (neon_vshl): Likewise. (neon_vqshl): Likewise. (neon_vshr_n): Likewise. (neon_vshrn_n): Likewise. (neon_vqshrn_n): Likewise. (neon_vqshrun_n): Likewise. (neon_vshl_n): Likewise. (neon_vqshl_n): Likewise. (neon_vqshlu_n): Likewise. (neon_vshll_n): Likewise. (neon_vsra_n): Likewise. (neon_vsri_n): Likewise. (neon_vsli_n): Likewise. (neon_vtbl1v8qi): Likewise. (neon_vtbl2v8qi): Likewise. (neon_vtbl3v8qi): Likewise. (neon_vtbl4v8qi): Likewise. (neon_vtbx1v8qi): Likewise. (neon_vtbx2v8qi): Likewise. (neon_vtbx3v8qi): Likewise. (neon_vtbx4v8qi): Likewise. (neon_vtrn_internal): Likewise. (neon_vzip_internal): Likewise. (neon_vuzp_internal): Likewise. (neon_vld1): Likewise. (neon_vld1_lane): Likewise. (neon_vld1_dup): Likewise. (neon_vld1_dupv2di): Likewise. (neon_vst1): Likewise. (neon_vst1_lane): Likewise. (neon_vld2): Likewise. (neon_vld2_lane): Likewise. (neon_vld2_dup): Likewise. (neon_vst2): Likewise. (neon_vst2_lane): Likewise. (neon_vld3): Likewise. (neon_vld3qa): Likewise. (neon_vld3qb): Likewise. (neon_vld3_lane): Likewise. (neon_vld3_dup): Likewise. (neon_vst3): Likewise. (neon_vst3qa): Likewise. (neon_vst3qb): Likewise. (neon_vst3_lane): Likewise. (neon_vld4): Likewise. (neon_vld4qa): Likewise. (neon_vld4qb): Likewise. (neon_vld4_lane): Likewise. (neon_vld4_dup): Likewise. (neon_vst4): Likewise. (neon_vst4qa): Likewise. (neon_vst4qb): Likewise. (neon_vst4_lane): Likewise. (neon_vec_unpack_lo_): Likewise. (neon_vec_unpack_hi_): Likewise. (neon_vec_mult_lo_): Likewise. (neon_vec_mult_hi_): Likewise. (neon_vec_shiftl_): Likewise. (neon_unpack_): Likewise. (neon_vec_mult_): Likewise. (vec_pack_trunc_): Likewise. (neon_vec_pack_trunk_): Likewise. (neon_vabd_2): Likewise. (neon_vabd_3): Likewise. * config/arm/types.md (type): Add Neon types. * config/arm/vfp.md (arm_movsi_vfp): Update for attribute changes. (thumb2_movsi_vfp): Likewise. (movdi_vfp): Likewise. (movdi_vfp_cortexa8): Likewise. (movhf_vfp_neon): Likewise. (movhf_vfp): Likewiwse. (movsf_vfp): Likewiwse. (thumb2_movsf_vfp): Likewiwse. (movdf_vfp): Likewise. (thumb2_movdf_vfp): Likewise. (movsfcc_vfp): Likewise. (thumb2_movsfcc_vfp): Likewise. (movdfcc_vfp): Likewise. (thumb2_movdfcc_vfp): Likewise. * config/arm/vfp11.md (vfp_fload): Update for attribute change. (vfp_fstore): Likewise. * doc/md.texi: Change references to neon_type to refer to type. --------------1.8.3-rc0 Content-Type: text/x-patch; name="0001-AArch64-AArch32-Insn-classification-refactoring-6-N-.patch" Content-Transfer-Encoding: 8bit Content-Disposition: attachment; filename="0001-AArch64-AArch32-Insn-classification-refactoring-6-N-.patch" diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 47532fca2c550e8ec9b63898511ef6c276943a45..d0321b3ef73f521294975e6d353a89c766ce001a 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -909,7 +909,7 @@ (define_insn "*movti_aarch64" str\\t%q1, %0" [(set_attr "v8type" "move2,fmovi2f,fmovf2i,*, \ load2,store2,store2,fpsimd_load,fpsimd_store") - (set_attr "type" "mov_reg,r_2_f,f_2_r,*, \ + (set_attr "type" "mov_reg,f_mcr,f_mrc,*, \ load2,store2,store2,f_loadd,f_stored") (set_attr "simd_type" "*,*,*,simd_move,*,*,*,*,*") (set_attr "mode" "DI,DI,DI,TI,DI,DI,DI,TI,TI") @@ -964,7 +964,7 @@ (define_insn "*movsf_aarch64" [(set_attr "v8type" "fmovi2f,fmovf2i,\ fmov,fconst,fpsimd_load,\ fpsimd_store,fpsimd_load,fpsimd_store,fmov") - (set_attr "type" "r_2_f,f_2_r,mov_reg,fconsts,\ + (set_attr "type" "f_mcr,f_mrc,mov_reg,fconsts,\ f_loads,f_stores,f_loads,f_stores,mov_reg") (set_attr "mode" "SF")] ) @@ -987,7 +987,7 @@ (define_insn "*movdf_aarch64" [(set_attr "v8type" "fmovi2f,fmovf2i,\ fmov,fconst,fpsimd_load,\ fpsimd_store,fpsimd_load,fpsimd_store,move") - (set_attr "type" "r_2_f,f_2_r,mov_reg,fconstd,\ + (set_attr "type" "f_mcr,f_mrc,mov_reg,fconstd,\ f_loadd,f_stored,f_loadd,f_stored,mov_reg") (set_attr "mode" "DF")] ) @@ -1027,7 +1027,7 @@ (define_insn "*movtf_aarch64" ldp\\t%0, %H0, %1 stp\\t%1, %H1, %0" [(set_attr "v8type" "logic,move2,fmovi2f,fmovf2i,fconst,fconst,fpsimd_load,fpsimd_store,fpsimd_load2,fpsimd_store2") - (set_attr "type" "arlo_reg,mov_reg,r_2_f,f_2_r,fconstd,fconstd,\ + (set_attr "type" "arlo_reg,mov_reg,f_mcr,f_mrc,fconstd,fconstd,\ f_loadd,f_stored,f_loadd,f_stored") (set_attr "mode" "DF,DF,DF,DF,DF,DF,TF,TF,DF,DF") (set_attr "length" "4,8,8,8,4,4,4,4,4,4") @@ -4031,7 +4031,7 @@ (define_insn "aarch64_movdi_low" "reload_completed || reload_in_progress" "fmov\\t%x0, %d1" [(set_attr "v8type" "fmovf2i") - (set_attr "type" "f_2_r") + (set_attr "type" "f_mrc") (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -4044,7 +4044,7 @@ (define_insn "aarch64_movdi_high" "reload_completed || reload_in_progress" "fmov\\t%x0, %1.d[1]" [(set_attr "v8type" "fmovf2i") - (set_attr "type" "f_2_r") + (set_attr "type" "f_mrc") (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -4056,7 +4056,7 @@ (define_insn "aarch64_movhigh_di" "reload_completed || reload_in_progress" "fmov\\t%0.d[1], %x1" [(set_attr "v8type" "fmovi2f") - (set_attr "type" "r_2_f") + (set_attr "type" "f_mcr") (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -4067,7 +4067,7 @@ (define_insn "aarch64_movlow_di" "reload_completed || reload_in_progress" "fmov\\t%d0, %x1" [(set_attr "v8type" "fmovi2f") - (set_attr "type" "r_2_f") + (set_attr "type" "f_mcr") (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -4079,7 +4079,7 @@ (define_insn "aarch64_movtilow_tilow" "reload_completed || reload_in_progress" "fmov\\t%d0, %d1" [(set_attr "v8type" "fmovi2f") - (set_attr "type" "r_2_f") + (set_attr "type" "f_mcr") (set_attr "mode" "DI") (set_attr "length" "4") ]) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index f731bb6..d310a7c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -8975,7 +8975,8 @@ cortexa7_older_only (rtx insn) case TYPE_FMACD: case TYPE_FDIVS: case TYPE_FDIVD: - case TYPE_F_2_R: + case TYPE_F_MRC: + case TYPE_F_MRRC: case TYPE_F_FLAG: case TYPE_F_LOADS: case TYPE_F_STORES: diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 45e9ada3d8ec71315a387e8275247c7402000c37..744f60607cbb4d31c82e81f8de2d78af97e05086 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -252,73 +252,6 @@ (define_asm_attributes ; initialized by arm_option_override() (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched"))) -;; Classification of NEON instructions for scheduling purposes. -(define_attr "neon_type" - "neon_int_1,\ - neon_int_2,\ - neon_int_3,\ - neon_int_4,\ - neon_int_5,\ - neon_vqneg_vqabs,\ - neon_vmov,\ - neon_vaba,\ - neon_vsma,\ - neon_vaba_qqq,\ - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ - neon_mul_qqq_8_16_32_ddd_32,\ - neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\ - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ - neon_mla_qqq_8_16,\ - neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\ - neon_mla_qqq_32_qqd_32_scalar,\ - neon_mul_ddd_16_scalar_32_16_long_scalar,\ - neon_mul_qqd_32_scalar,\ - neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\ - neon_shift_1,\ - neon_shift_2,\ - neon_shift_3,\ - neon_vshl_ddd,\ - neon_vqshl_vrshl_vqrshl_qqq,\ - neon_vsra_vrsra,\ - neon_fp_vadd_ddd_vabs_dd,\ - neon_fp_vadd_qqq_vabs_qq,\ - neon_fp_vsum,\ - neon_fp_vmul_ddd,\ - neon_fp_vmul_qqd,\ - neon_fp_vmla_ddd,\ - neon_fp_vmla_qqq,\ - neon_fp_vmla_ddd_scalar,\ - neon_fp_vmla_qqq_scalar,\ - neon_fp_vrecps_vrsqrts_ddd,\ - neon_fp_vrecps_vrsqrts_qqq,\ - neon_bp_simple,\ - neon_bp_2cycle,\ - neon_bp_3cycle,\ - neon_ldr,\ - neon_str,\ - neon_vld1_1_2_regs,\ - neon_vld1_3_4_regs,\ - neon_vld2_2_regs_vld1_vld2_all_lanes,\ - neon_vld2_4_regs,\ - neon_vld3_vld4,\ - neon_vst1_1_2_regs_vst2_2_regs,\ - neon_vst1_3_4_regs,\ - neon_vst2_4_regs_vst3_vst4,\ - neon_vst3_vst4,\ - neon_vld1_vld2_lane,\ - neon_vld3_vld4_lane,\ - neon_vst1_vst2_lane,\ - neon_vst3_vst4_lane,\ - neon_vld3_vld4_all_lanes,\ - neon_mcr,\ - neon_mcr_2_mcrr,\ - neon_mrc,\ - neon_mrrc,\ - neon_ldm_2,\ - neon_stm_2,\ - none" - (const_string "none")) - ; condition codes: this one is used by final_prescan_insn to speed up ; conditionalizing instructions. It saves having to scan the rtl to see if ; it uses or alters the condition codes. @@ -344,9 +277,34 @@ (define_attr "conds" "use,set,clob,uncon (ior (eq_attr "is_thumb1" "yes") (eq_attr "type" "call")) (const_string "clob") - (if_then_else (eq_attr "neon_type" "none") - (const_string "nocond") - (const_string "unconditional")))) + (if_then_else (eq_attr "type" + "!neon_int_1, neon_int_2, neon_int_3, neon_int_4, neon_int_5,\ + neon_vqneg_vqabs, neon_vmov, neon_vaba, neon_vsma, neon_vaba_qqq,\ + neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ + neon_mul_qqq_8_16_32_ddd_32,\ + neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\ + neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ + neon_mla_qqq_8_16,\ + neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\ + neon_mla_qqq_32_qqd_32_scalar,\ + neon_mul_ddd_16_scalar_32_16_long_scalar, neon_mul_qqd_32_scalar,\ + neon_mla_ddd_16_scalar_qdd_32_16_long_scalar, neon_shift_1,\ + neon_shift_2, neon_shift_3, neon_vshl_ddd,\ + neon_vqshl_vrshl_vqrshl_qqq, neon_vsra_vrsra,\ + neon_fp_vadd_ddd_vabs_dd, neon_fp_vadd_qqq_vabs_qq, neon_fp_vsum,\ + neon_fp_vmul_ddd, neon_fp_vmul_qqd, neon_fp_vmla_ddd,\ + neon_fp_vmla_qqq, neon_fp_vmla_ddd_scalar, neon_fp_vmla_qqq_scalar,\ + neon_fp_vrecps_vrsqrts_ddd, neon_fp_vrecps_vrsqrts_qqq,\ + neon_bp_simple, neon_bp_2cycle, neon_bp_3cycle, neon_ldr, neon_str,\ + neon_vld1_1_2_regs, neon_vld1_3_4_regs,\ + neon_vld2_2_regs_vld1_vld2_all_lanes, neon_vld2_4_regs,\ + neon_vld3_vld4, neon_vst1_1_2_regs_vst2_2_regs, neon_vst1_3_4_regs,\ + neon_vst2_4_regs_vst3_vst4, neon_vst3_vst4, neon_vld1_vld2_lane,\ + neon_vld3_vld4_lane, neon_vst1_vst2_lane, neon_vst3_vst4_lane,\ + neon_vld3_vld4_all_lanes, neon_mcr, neon_mcr_2_mcrr, neon_mrc,\ + neon_mrrc, neon_ldm_2, neon_stm_2") + (const_string "nocond") + (const_string "unconditional")))) ; Predicable means that the insn can be conditionally executed based on ; an automatically added predicate (additional patterns are generated by @@ -2179,7 +2137,7 @@ (define_insn_and_split "*anddi3_insn" gen_highpart_mode (SImode, DImode, operands[2])); }" - [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1") + [(set_attr "type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1") (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*, avoid_neon_for_64bits,avoid_neon_for_64bits") (set_attr "length" "*,*,8,8,8,8,*,*") @@ -3014,7 +2972,7 @@ (define_insn_and_split "*iordi3_insn" gen_highpart_mode (SImode, DImode, operands[2])); }" - [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1") + [(set_attr "type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1") (set_attr "length" "*,*,8,8,8,8,*,*") (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")] ) @@ -3193,7 +3151,7 @@ (define_insn_and_split "*xordi3_insn" }" [(set_attr "length" "*,8,8,8,8,*") - (set_attr "neon_type" "neon_int_1,*,*,*,*,neon_int_1") + (set_attr "type" "neon_int_1,*,*,*,*,neon_int_1") (set_attr "arch" "neon_for_64bits,*,*,*,*,avoid_neon_for_64bits")] ) @@ -4960,7 +4918,7 @@ (define_insn_and_split "one_cmpldi2" }" [(set_attr "length" "*,8,8,*") (set_attr "predicable" "no,yes,yes,no") - (set_attr "neon_type" "neon_int_1,*,*,neon_int_1") + (set_attr "type" "neon_int_1,*,*,neon_int_1") (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")] ) diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md index 317e4cd4ad6f635d390a62bbbd9345cf00d5563e..3a5e08fb7e5c079afa6e769e11d569bef30784ce 100644 --- a/gcc/config/arm/arm1020e.md +++ b/gcc/config/arm/arm1020e.md @@ -316,7 +316,7 @@ (define_insn_reservation "v10_floadd" 5 (define_insn_reservation "v10_c2v" 4 (and (eq_attr "vfp10" "yes") - (eq_attr "type" "r_2_f")) + (eq_attr "type" "f_mcr,f_mcrr")) "1020a_e+1020l_e+v10_ls1,v10_ls2") (define_insn_reservation "v10_fstores" 1 @@ -331,7 +331,7 @@ (define_insn_reservation "v10_fstored" 1 (define_insn_reservation "v10_v2c" 1 (and (eq_attr "vfp10" "yes") - (eq_attr "type" "f_2_r")) + (eq_attr "type" "f_mrc,f_mrrc")) "1020a_e+1020l_e,1020l_m,1020l_w") (define_insn_reservation "v10_to_cpsr" 2 diff --git a/gcc/config/arm/cortex-a15-neon.md b/gcc/config/arm/cortex-a15-neon.md index bfa2f5e8818f046439b33c6e76d09f547297da87..f1cac9e1af88bd5e3f0d87ff50c44376ad82d441 100644 --- a/gcc/config/arm/cortex-a15-neon.md +++ b/gcc/config/arm/cortex-a15-neon.md @@ -93,389 +93,345 @@ (define_reservation "ca15_cx_perm_2" "ca (define_insn_reservation "cortex_a15_neon_int_1" 5 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" "neon_int_1")) + (eq_attr "type" "neon_int_1")) "ca15_issue1,ca15_cx_ialu") (define_insn_reservation "cortex_a15_neon_int_2" 5 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" "neon_int_2")) + (eq_attr "type" "neon_int_2")) "ca15_issue1,ca15_cx_ialu") (define_insn_reservation "cortex_a15_neon_int_3" 5 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" "neon_int_3")) + (eq_attr "type" "neon_int_3")) "ca15_issue1,ca15_cx_ialu") (define_insn_reservation "cortex_a15_neon_int_4" 5 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" "neon_int_4")) + (eq_attr "type" "neon_int_4")) "ca15_issue1,ca15_cx_ialu") (define_insn_reservation "cortex_a15_neon_int_5" 5 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" "neon_int_5")) + (eq_attr "type" "neon_int_5")) "ca15_issue1,ca15_cx_ialu") (define_insn_reservation "cortex_a15_neon_vqneg_vqabs" 5 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" "neon_vqneg_vqabs")) + (eq_attr "type" "neon_vqneg_vqabs")) "ca15_issue1,ca15_cx_ialu") (define_insn_reservation "cortex_a15_neon_vmov" 5 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" "neon_vmov")) + (eq_attr "type" "neon_vmov")) "ca15_issue1,ca15_cx_ialu") (define_insn_reservation "cortex_a15_neon_vaba" 7 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" "neon_vaba")) + (eq_attr "type" "neon_vaba")) "ca15_issue1,ca15_cx_ialu_with_acc") (define_insn_reservation "cortex_a15_neon_vaba_qqq" 8 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" "neon_vaba_qqq")) + (eq_attr "type" "neon_vaba_qqq")) "ca15_issue2,ca15_cx_ialu_with_acc*2") (define_insn_reservation "cortex_a15_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) + (eq_attr "type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) "ca15_issue1,ca15_cx_imac") (define_insn_reservation "cortex_a15_neon_mul_qqq_8_16_32_ddd_32" 7 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32")) + (eq_attr "type" "neon_mul_qqq_8_16_32_ddd_32")) "ca15_issue1,ca15_cx_imac*2") (define_insn_reservation "cortex_a15_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" + (eq_attr "type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")) "ca15_issue1,ca15_cx_imac*2") (define_insn_reservation "cortex_a15_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" + (eq_attr "type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")) "ca15_issue1,ca15_cx_imac") (define_insn_reservation "cortex_a15_neon_mla_qqq_8_16" 7 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" + (eq_attr "type" "neon_mla_qqq_8_16")) "ca15_issue1,ca15_cx_imac*2") (define_insn_reservation "cortex_a15_neon_mla_ddd_32_qqd_16_ddd_32_scalar_\ - qdd_64_32_long_scalar_qdd_64_32_long" 7 + qdd_64_32_lotype_qdd_64_32_long" 7 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) + (eq_attr "type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) "ca15_issue1,ca15_cx_imac") (define_insn_reservation "cortex_a15_neon_mla_qqq_32_qqd_32_scalar" 7 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_mla_qqq_32_qqd_32_scalar")) + (eq_attr "type" "neon_mla_qqq_32_qqd_32_scalar")) "ca15_issue1,ca15_cx_imac*2") (define_insn_reservation "cortex_a15_neon_mul_ddd_16_scalar_32_16_long_scalar" 6 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_mul_ddd_16_scalar_32_16_long_scalar")) + (eq_attr "type" "neon_mul_ddd_16_scalar_32_16_long_scalar")) "ca15_issue1,ca15_cx_imac") (define_insn_reservation "cortex_a15_neon_mul_qqd_32_scalar" 7 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_mul_qqd_32_scalar")) + (eq_attr "type" "neon_mul_qqd_32_scalar")) "ca15_issue1,ca15_cx_imac*2") (define_insn_reservation "cortex_a15_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) + (eq_attr "type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) "ca15_issue1,ca15_cx_imac") (define_insn_reservation "cortex_a15_neon_shift_1" 5 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_shift_1")) + (eq_attr "type" "neon_shift_1")) "ca15_issue1,ca15_cx_ik+ca15_cx_ishf") (define_insn_reservation "cortex_a15_neon_shift_2" 5 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_shift_2")) + (eq_attr "type" "neon_shift_2")) "ca15_issue1,ca15_cx_ik+ca15_cx_ishf") (define_insn_reservation "cortex_a15_neon_shift_3" 6 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_shift_3")) + (eq_attr "type" "neon_shift_3")) "ca15_issue2,(ca15_cx_ik+ca15_cx_ishf)*2") (define_insn_reservation "cortex_a15_neon_vshl_ddd" 5 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vshl_ddd")) + (eq_attr "type" "neon_vshl_ddd")) "ca15_issue1,ca15_cx_ik+ca15_cx_ishf") (define_insn_reservation "cortex_a15_neon_vqshl_vrshl_vqrshl_qqq" 6 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vqshl_vrshl_vqrshl_qqq")) + (eq_attr "type" "neon_vqshl_vrshl_vqrshl_qqq")) "ca15_issue2,(ca15_cx_ik+ca15_cx_ishf)*2") (define_insn_reservation "cortex_a15_neon_vsra_vrsra" 7 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vsra_vrsra")) + (eq_attr "type" "neon_vsra_vrsra")) "ca15_issue1,ca15_cx_ishf_with_acc") (define_insn_reservation "cortex_a15_neon_fp_vadd_ddd_vabs_dd" 6 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_fp_vadd_ddd_vabs_dd")) + (eq_attr "type" "neon_fp_vadd_ddd_vabs_dd")) "ca15_issue1,ca15_cx_falu") (define_insn_reservation "cortex_a15_neon_fp_vadd_qqq_vabs_qq" 7 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_fp_vadd_qqq_vabs_qq")) + (eq_attr "type" "neon_fp_vadd_qqq_vabs_qq")) "ca15_issue2,ca15_cx_falu_2") (define_insn_reservation "cortex_a15_neon_fp_vmul_ddd" 5 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_fp_vmul_ddd")) + (eq_attr "type" "neon_fp_vmul_ddd")) "ca15_issue1,ca15_cx_fmul") (define_insn_reservation "cortex_a15_neon_fp_vmul_qqd" 6 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_fp_vmul_qqd")) + (eq_attr "type" "neon_fp_vmul_qqd")) "ca15_issue2,ca15_cx_fmul_2") (define_insn_reservation "cortex_a15_neon_fp_vmla_ddd" 9 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_fp_vmla_ddd")) + (eq_attr "type" "neon_fp_vmla_ddd")) "ca15_issue1,ca15_cx_fmac") (define_insn_reservation "cortex_a15_neon_fp_vmla_qqq" 11 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_fp_vmla_qqq")) + (eq_attr "type" "neon_fp_vmla_qqq")) "ca15_issue2,ca15_cx_fmac_2") (define_insn_reservation "cortex_a15_neon_fp_vmla_ddd_scalar" 9 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_fp_vmla_ddd_scalar")) + (eq_attr "type" "neon_fp_vmla_ddd_scalar")) "ca15_issue1,ca15_cx_fmac") (define_insn_reservation "cortex_a15_neon_fp_vmla_qqq_scalar" 11 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_fp_vmla_qqq_scalar")) + (eq_attr "type" "neon_fp_vmla_qqq_scalar")) "ca15_issue2,ca15_cx_fmac_2") (define_insn_reservation "cortex_a15_neon_fp_vrecps_vrsqrts_ddd" 9 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_fp_vrecps_vrsqrts_ddd")) + (eq_attr "type" "neon_fp_vrecps_vrsqrts_ddd")) "ca15_issue1,ca15_cx_fmac") (define_insn_reservation "cortex_a15_neon_fp_vrecps_vrsqrts_qqq" 11 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_fp_vrecps_vrsqrts_qqq")) + (eq_attr "type" "neon_fp_vrecps_vrsqrts_qqq")) "ca15_issue2,ca15_cx_fmac_2") (define_insn_reservation "cortex_a15_neon_bp_simple" 4 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_bp_simple")) + (eq_attr "type" "neon_bp_simple")) "ca15_issue3,ca15_ls+ca15_cx_perm_2,ca15_cx_perm") (define_insn_reservation "cortex_a15_neon_bp_2cycle" 4 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_bp_2cycle")) + (eq_attr "type" "neon_bp_2cycle")) "ca15_issue1,ca15_cx_perm") (define_insn_reservation "cortex_a15_neon_bp_3cycle" 7 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_bp_3cycle")) + (eq_attr "type" "neon_bp_3cycle")) "ca15_issue3,ca15_cx_ialu+ca15_cx_perm_2,ca15_cx_perm") (define_insn_reservation "cortex_a15_neon_vld1_1_2_regs" 7 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vld1_1_2_regs")) + (eq_attr "type" "neon_vld1_1_2_regs")) "ca15_issue2,ca15_ls,ca15_ldr") (define_insn_reservation "cortex_a15_neon_vld1_3_4_regs" 8 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vld1_3_4_regs")) + (eq_attr "type" "neon_vld1_3_4_regs")) "ca15_issue3,ca15_ls1+ca15_ls2,ca15_ldr,ca15_ldr") (define_insn_reservation "cortex_a15_neon_vld2_2_regs_vld1_vld2_all_lanes" 9 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vld2_2_regs_vld1_vld2_all_lanes")) + (eq_attr "type" "neon_vld2_2_regs_vld1_vld2_all_lanes")) "ca15_issue3,ca15_ls,ca15_ldr") (define_insn_reservation "cortex_a15_neon_vld2_4_regs" 12 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vld2_4_regs")) + (eq_attr "type" "neon_vld2_4_regs")) "ca15_issue3,ca15_issue3+ca15_ls1+ca15_ls2,ca15_ldr*2") (define_insn_reservation "cortex_a15_neon_vld3_vld4" 12 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vld3_vld4")) + (eq_attr "type" "neon_vld3_vld4")) "ca15_issue3,ca15_issue3+ca15_ls1+ca15_ls2,ca15_ldr*2") (define_insn_reservation "cortex_a15_neon_vst1_1_2_regs_vst2_2_regs" 0 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vst1_1_2_regs_vst2_2_regs")) + (eq_attr "type" "neon_vst1_1_2_regs_vst2_2_regs")) "ca15_issue3,ca15_issue3+ca15_cx_perm+ca15_ls1+ca15_ls2,ca15_str*2") (define_insn_reservation "cortex_a15_neon_vst1_3_4_regs" 0 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vst1_3_4_regs")) + (eq_attr "type" "neon_vst1_3_4_regs")) "ca15_issue3,ca15_issue3+ca15_ls1+ca15_ls2,ca15_str*3") (define_insn_reservation "cortex_a15_neon_vst2_4_regs_vst3_vst4" 0 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vst2_4_regs_vst3_vst4")) + (eq_attr "type" "neon_vst2_4_regs_vst3_vst4")) "ca15_issue3,ca15_issue3+ca15_cx_perm_2+ca15_ls1+ca15_ls2,\ ca15_issue3+ca15_str,ca15_str*3") (define_insn_reservation "cortex_a15_neon_vst3_vst4" 0 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vst3_vst4")) + (eq_attr "type" "neon_vst3_vst4")) "ca15_issue3,ca15_issue3+ca15_cx_perm_2+ca15_ls1+ca15_ls2,ca15_str*4") (define_insn_reservation "cortex_a15_neon_vld1_vld2_lane" 9 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vld1_vld2_lane")) + (eq_attr "type" "neon_vld1_vld2_lane")) "ca15_issue3,ca15_ls,ca15_ldr") (define_insn_reservation "cortex_a15_neon_vld3_vld4_lane" 10 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vld3_vld4_lane")) + (eq_attr "type" "neon_vld3_vld4_lane")) "ca15_issue3,ca15_issue3+ca15_ls,ca15_issue3+ca15_ldr") (define_insn_reservation "cortex_a15_neon_vst1_vst2_lane" 0 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vst1_vst2_lane")) + (eq_attr "type" "neon_vst1_vst2_lane")) "ca15_issue3,ca15_cx_perm+ca15_ls,ca15_str") (define_insn_reservation "cortex_a15_neon_vst3_vst4_lane" 0 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vst3_vst4_lane")) + (eq_attr "type" "neon_vst3_vst4_lane")) "ca15_issue3,ca15_issue3+ca15_cx_perm+ca15_ls1+ca15_ls2,ca15_str*2") (define_insn_reservation "cortex_a15_neon_vld3_vld4_all_lanes" 11 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_vld3_vld4_all_lanes")) + (eq_attr "type" "neon_vld3_vld4_all_lanes")) "ca15_issue3,ca15_issue3+ca15_ls,ca15_ldr") (define_insn_reservation "cortex_a15_neon_ldm_2" 20 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_ldm_2")) + (eq_attr "type" "neon_ldm_2")) "ca15_issue3*6") (define_insn_reservation "cortex_a15_neon_stm_2" 0 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_stm_2")) + (eq_attr "type" "neon_stm_2")) "ca15_issue3*6") (define_insn_reservation "cortex_a15_neon_mcr" 6 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_mcr")) + (eq_attr "type" "neon_mcr")) "ca15_issue2,ca15_ls,ca15_cx_perm") (define_insn_reservation "cortex_a15_neon_mcr_2_mcrr" 6 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_mcr_2_mcrr")) + (eq_attr "type" "neon_mcr_2_mcrr")) "ca15_issue2,ca15_ls1+ca15_ls2") (define_insn_reservation "cortex_a15_neon_mrc" 5 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_mrc")) + (eq_attr "type" "neon_mrc")) "ca15_issue1,ca15_ls") (define_insn_reservation "cortex_a15_neon_mrrc" 6 (and (eq_attr "tune" "cortexa15") - (eq_attr "neon_type" - "neon_mrrc")) + (eq_attr "type" "neon_mrrc")) "ca15_issue2,ca15_ls1+ca15_ls2") (define_insn_reservation "cortex_a15_vfp_const" 4 diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md index 4ad87121d6dbb6e2514d301aaa3bcf674026d562..a816e29a3cbde6eb1859f266bf662a5d71584ec1 100644 --- a/gcc/config/arm/cortex-a15.md +++ b/gcc/config/arm/cortex-a15.md @@ -61,25 +61,22 @@ (define_cpu_unit "ca15_sx2_alu, ca15_sx2 ;; Simple ALU without shift (define_insn_reservation "cortex_a15_alu" 2 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ mov_imm,mov_reg,\ - mvn_imm,mvn_reg") - (eq_attr "neon_type" "none"))) + mvn_imm,mvn_reg")) "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)") ;; ALU ops with immediate shift (define_insn_reservation "cortex_a15_alu_shift" 3 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "extend,arlo_shift,,mov_shift,mvn_shift") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "extend,arlo_shift,,mov_shift,mvn_shift")) "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\ |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)") ;; ALU ops with register controlled shift (define_insn_reservation "cortex_a15_alu_shift_reg" 3 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")) "(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\ |(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\ |(ca15_issue1+ca15_sx1,ca15_sx1+ca15_sx1_shf),ca15_sx1_alu)") @@ -89,15 +86,13 @@ (define_insn_reservation "cortex_a15_alu ;; 32-bit multiplies (define_insn_reservation "cortex_a15_mult32" 3 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "mul32" "yes") - (eq_attr "neon_type" "none"))) + (eq_attr "mul32" "yes")) "ca15_issue1,ca15_mx") ;; 64-bit multiplies (define_insn_reservation "cortex_a15_mult64" 4 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "mul64" "yes") - (eq_attr "neon_type" "none"))) + (eq_attr "mul64" "yes")) "ca15_issue1,ca15_mx*2") ;; Integer divide @@ -114,8 +109,7 @@ (define_insn_reservation "cortex_a15_sdi ;; Block all issue pipes for a cycle (define_insn_reservation "cortex_a15_block" 1 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "block") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "block")) "ca15_issue3") ;; Branch execution Unit @@ -124,8 +118,7 @@ (define_insn_reservation "cortex_a15_blo ;; No latency as there is no result (define_insn_reservation "cortex_a15_branch" 0 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "branch") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "branch")) "ca15_issue1,ca15_bx") ;; Load-store execution Unit @@ -133,29 +126,25 @@ (define_insn_reservation "cortex_a15_bra ;; Loads of up to two words. (define_insn_reservation "cortex_a15_load1" 4 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "load_byte,load1,load2") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "load_byte,load1,load2")) "ca15_issue1,ca15_ls,ca15_ldr,nothing") ;; Loads of three or four words. (define_insn_reservation "cortex_a15_load3" 5 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "load3,load4") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "load3,load4")) "ca15_issue2,ca15_ls1+ca15_ls2,ca15_ldr,ca15_ldr,nothing") ;; Stores of up to two words. (define_insn_reservation "cortex_a15_store1" 0 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "store1,store2") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "store1,store2")) "ca15_issue1,ca15_ls,ca15_str") ;; Stores of three or four words. (define_insn_reservation "cortex_a15_store3" 0 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "store3,store4") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "store3,store4")) "ca15_issue2,ca15_ls1+ca15_ls2,ca15_str,ca15_str") ;; We include Neon.md here to ensure that the branch can block the Neon units. @@ -165,8 +154,7 @@ (define_insn_reservation "cortex_a15_sto ;; pipeline. The result however is available the next cycle. (define_insn_reservation "cortex_a15_call" 1 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "call") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "call")) "ca15_issue3,\ ca15_sx1+ca15_sx2+ca15_bx+ca15_mx+ca15_cx_ij+ca15_cx_ik+ca15_ls1+ca15_ls2+\ ca15_cx_imac1+ca15_cx_ialu1+ca15_cx_ialu2+ca15_cx_ishf+\ diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md index 1400c47d95a91417e1e0792b446536618ec43c78..67f641c174bc9e3f4379f0b0709ce6ddafab2378 100644 --- a/gcc/config/arm/cortex-a5.md +++ b/gcc/config/arm/cortex-a5.md @@ -243,12 +243,12 @@ (define_insn_reservation "cortex_a5_fdiv (define_insn_reservation "cortex_a5_r2f" 4 (and (eq_attr "tune" "cortexa5") - (eq_attr "type" "r_2_f")) + (eq_attr "type" "f_mcr,f_mcrr")) "cortex_a5_ex1") (define_insn_reservation "cortex_a5_f2r" 2 (and (eq_attr "tune" "cortexa5") - (eq_attr "type" "f_2_r")) + (eq_attr "type" "f_mrc,f_mrrc")) "cortex_a5_ex1") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index 39a95286e086ee6b4869f82ab94a13ec836cb5ad..5bb8ab02a331eff598bb1debc28d1f389a593d1c 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -244,12 +244,12 @@ (define_insn_reservation "cortex_a53_fdi (define_insn_reservation "cortex_a53_r2f" 4 (and (eq_attr "tune" "cortexa53") - (eq_attr "type" "r_2_f")) + (eq_attr "type" "f_mcr,f_mcrr")) "cortex_a53_slot0") (define_insn_reservation "cortex_a53_f2r" 2 (and (eq_attr "tune" "cortexa53") - (eq_attr "type" "f_2_r")) + (eq_attr "type" "f_mrc,f_mrrc")) "cortex_a53_slot0") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md index e14413d5083a206052ee9c63a0b67fb336c1bc6f..cb1f7cff2642e83d058ee75d6b67461982523c45 100644 --- a/gcc/config/arm/cortex-a7.md +++ b/gcc/config/arm/cortex-a7.md @@ -67,8 +67,7 @@ (define_cpu_unit "cortex_a7_fp_div_sqrt" (define_insn_reservation "cortex_a7_branch" 0 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "branch") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "branch")) "(cortex_a7_ex2|cortex_a7_ex1)+cortex_a7_branch") ;; Call cannot dual-issue as an older instruction. It can dual-issue @@ -77,8 +76,7 @@ (define_insn_reservation "cortex_a7_bran ;; cycle. (define_insn_reservation "cortex_a7_call" 1 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "call") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "call")) "(cortex_a7_ex2|cortex_a7_both)+cortex_a7_branch") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -88,27 +86,23 @@ (define_insn_reservation "cortex_a7_call ;; ALU instruction with an immediate operand can dual-issue. (define_insn_reservation "cortex_a7_alu_imm" 2 (and (eq_attr "tune" "cortexa7") - (and (ior (eq_attr "type" "arlo_imm,mov_imm,mvn_imm") - (ior (eq_attr "type" "extend") - (and (eq_attr "type" "mov_reg,mov_shift,mov_shift_reg") - (not (eq_attr "length" "8"))))) - (eq_attr "neon_type" "none"))) + (ior (eq_attr "type" "arlo_imm,mov_imm,mvn_imm,extend") + (and (eq_attr "type" "mov_reg,mov_shift,mov_shift_reg") + (not (eq_attr "length" "8"))))) "cortex_a7_ex2|cortex_a7_ex1") ;; ALU instruction with register operands can dual-issue ;; with a younger immediate-based instruction. (define_insn_reservation "cortex_a7_alu_reg" 2 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "arlo_reg,shift,shift_reg,mov_reg,mvn_reg") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "arlo_reg,shift,shift_reg,mov_reg,mvn_reg")) "cortex_a7_ex1") (define_insn_reservation "cortex_a7_alu_shift" 2 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "arlo_shift,arlo_shift_reg,\ - mov_shift,mov_shift_reg,\ - mvn_shift,mvn_shift_reg") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "arlo_shift,arlo_shift_reg,\ + mov_shift,mov_shift_reg,\ + mvn_shift,mvn_shift_reg")) "cortex_a7_ex1") ;; Forwarding path for unshifted operands. @@ -129,9 +123,8 @@ (define_bypass 1 "cortex_a7_alu_imm,cort (define_insn_reservation "cortex_a7_mul" 2 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "neon_type" "none") - (ior (eq_attr "mul32" "yes") - (eq_attr "mul64" "yes")))) + (ior (eq_attr "mul32" "yes") + (eq_attr "mul64" "yes"))) "cortex_a7_both") ;; Forward the result of a multiply operation to the accumulator @@ -156,50 +149,42 @@ (define_insn_reservation "cortex_a7_idiv (define_insn_reservation "cortex_a7_load1" 2 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "load_byte,load1") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "load_byte,load1")) "cortex_a7_ex1") (define_insn_reservation "cortex_a7_store1" 0 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "store1") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "store1")) "cortex_a7_ex1") (define_insn_reservation "cortex_a7_load2" 2 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "load2") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "load2")) "cortex_a7_both") (define_insn_reservation "cortex_a7_store2" 0 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "store2") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "store2")) "cortex_a7_both") (define_insn_reservation "cortex_a7_load3" 3 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "load3") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "load3")) "cortex_a7_both, cortex_a7_ex1") (define_insn_reservation "cortex_a7_store3" 0 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "store4") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "store4")) "cortex_a7_both, cortex_a7_ex1") (define_insn_reservation "cortex_a7_load4" 3 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "load4") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "load4")) "cortex_a7_both, cortex_a7_both") (define_insn_reservation "cortex_a7_store4" 0 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "store3") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "store3")) "cortex_a7_both, cortex_a7_both") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -211,9 +196,8 @@ (define_insn_reservation "cortex_a7_stor (define_insn_reservation "cortex_a7_fpalu" 4 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\ - f_cvt, fcmps, fcmpd") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\ + f_cvt, fcmps, fcmpd")) "cortex_a7_ex1+cortex_a7_fpadd_pipe") ;; For fconsts and fconstd, 8-bit immediate data is passed directly from @@ -221,8 +205,7 @@ (define_insn_reservation "cortex_a7_fpal (define_insn_reservation "cortex_a7_fconst" 3 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "fconsts,fconstd") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "fconsts,fconstd")) "cortex_a7_ex1+cortex_a7_fpadd_pipe") ;; We should try not to attempt to issue a single-precision multiplication in @@ -231,13 +214,12 @@ (define_insn_reservation "cortex_a7_fcon (define_insn_reservation "cortex_a7_fpmuls" 4 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "fmuls") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "fmuls")) "cortex_a7_ex1+cortex_a7_fpmul_pipe") (define_insn_reservation "cortex_a7_neon_mul" 4 (and (eq_attr "tune" "cortexa7") - (eq_attr "neon_type" + (eq_attr "type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ neon_mul_qqq_8_16_32_ddd_32,\ neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\ @@ -249,13 +231,12 @@ (define_insn_reservation "cortex_a7_neon (define_insn_reservation "cortex_a7_fpmacs" 8 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "fmacs,ffmas") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "fmacs,ffmas")) "cortex_a7_ex1+cortex_a7_fpmul_pipe") (define_insn_reservation "cortex_a7_neon_mla" 8 (and (eq_attr "tune" "cortexa7") - (eq_attr "neon_type" + (eq_attr "type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ neon_mla_qqq_8_16,\ neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\ @@ -276,20 +257,17 @@ (define_bypass 4 "cortex_a7_fpmacs,corte (define_insn_reservation "cortex_a7_fpmuld" 7 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "fmuld") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "fmuld")) "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3") (define_insn_reservation "cortex_a7_fpmacd" 11 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "fmacd") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "fmacd")) "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3") (define_insn_reservation "cortex_a7_fpfmad" 8 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "ffmad") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "ffmad")) "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*4") (define_bypass 7 "cortex_a7_fpmacd" @@ -302,14 +280,12 @@ (define_bypass 7 "cortex_a7_fpmacd" (define_insn_reservation "cortex_a7_fdivs" 16 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "fdivs") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "fdivs")) "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 13") (define_insn_reservation "cortex_a7_fdivd" 31 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "fdivd") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "fdivd")) "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 28") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -320,14 +296,12 @@ (define_insn_reservation "cortex_a7_fdiv (define_insn_reservation "cortex_a7_r2f" 4 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "r_2_f") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "f_mcr,f_mcrr")) "cortex_a7_both") (define_insn_reservation "cortex_a7_f2r" 2 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "f_2_r") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "f_mrc,f_mrrc")) "cortex_a7_ex1") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -339,8 +313,7 @@ (define_insn_reservation "cortex_a7_f2r" (define_insn_reservation "cortex_a7_f_flags" 4 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "f_flag") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "f_flag")) "cortex_a7_ex1") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -349,26 +322,22 @@ (define_insn_reservation "cortex_a7_f_fl (define_insn_reservation "cortex_a7_f_loads" 4 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "f_loads") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "f_loads")) "cortex_a7_ex1") (define_insn_reservation "cortex_a7_f_loadd" 4 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "f_loadd") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "f_loadd")) "cortex_a7_both") (define_insn_reservation "cortex_a7_f_stores" 0 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "f_stores") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "f_stores")) "cortex_a7_ex1") (define_insn_reservation "cortex_a7_f_stored" 0 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "f_stored") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "f_stored")) "cortex_a7_both") ;; Load-to-use for floating-point values has a penalty of one cycle, @@ -389,22 +358,21 @@ (define_bypass 2 "cortex_a7_f_loads, cor (define_insn_reservation "cortex_a7_neon" 4 (and (eq_attr "tune" "cortexa7") - (eq_attr "neon_type" - "!none,\ - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ - neon_mul_qqq_8_16_32_ddd_32,\ - neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\ - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ - neon_mla_qqq_8_16,\ - neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\ - neon_mla_qqq_32_qqd_32_scalar,\ - neon_mul_ddd_16_scalar_32_16_long_scalar,\ - neon_mul_qqd_32_scalar,\ - neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\ - neon_fp_vmul_ddd,\ - neon_fp_vmul_qqd,\ - neon_fp_vmla_ddd,\ - neon_fp_vmla_qqq,\ - neon_fp_vmla_ddd_scalar,\ - neon_fp_vmla_qqq_scalar")) + (eq_attr "type" + "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ + neon_mul_qqq_8_16_32_ddd_32,\ + neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\ + neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ + neon_mla_qqq_8_16,\ + neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\ + neon_mla_qqq_32_qqd_32_scalar,\ + neon_mul_ddd_16_scalar_32_16_long_scalar,\ + neon_mul_qqd_32_scalar,\ + neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\ + neon_fp_vmul_ddd,\ + neon_fp_vmul_qqd,\ + neon_fp_vmla_ddd,\ + neon_fp_vmla_qqq,\ + neon_fp_vmla_ddd_scalar,\ + neon_fp_vmla_qqq_scalar")) "cortex_a7_both*2") diff --git a/gcc/config/arm/cortex-a8-neon.md b/gcc/config/arm/cortex-a8-neon.md index 2f0cc7b3a5a9231a3c4a3a5e6abd3b6cac334581..57a81142a18f0c4381c13fecab07da49290b3fad 100644 --- a/gcc/config/arm/cortex-a8-neon.md +++ b/gcc/config/arm/cortex-a8-neon.md @@ -184,12 +184,12 @@ (define_insn_reservation "cortex_a8_vfp_ (define_insn_reservation "cortex_a8_neon_mrc" 20 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_mrc")) + (eq_attr "type" "neon_mrc")) "cortex_a8_neon_ls") (define_insn_reservation "cortex_a8_neon_mrrc" 21 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_mrrc")) + (eq_attr "type" "neon_mrrc")) "cortex_a8_neon_ls_2") ;; The remainder of this file is auto-generated by neon-schedgen. @@ -198,48 +198,48 @@ (define_insn_reservation "cortex_a8_neon ;; produce a result at N3. (define_insn_reservation "cortex_a8_neon_int_1" 3 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_int_1")) + (eq_attr "type" "neon_int_1")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their (D|Q)m operands at N1, ;; their (D|Q)n operands at N2, and produce a result at N3. (define_insn_reservation "cortex_a8_neon_int_2" 3 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_int_2")) + (eq_attr "type" "neon_int_2")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N3. (define_insn_reservation "cortex_a8_neon_int_3" 3 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_int_3")) + (eq_attr "type" "neon_int_3")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their source operands at N2, and ;; produce a result at N4. (define_insn_reservation "cortex_a8_neon_int_4" 4 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_int_4")) + (eq_attr "type" "neon_int_4")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their (D|Q)m operands at N1, ;; their (D|Q)n operands at N2, and produce a result at N4. (define_insn_reservation "cortex_a8_neon_int_5" 4 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_int_5")) + (eq_attr "type" "neon_int_5")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N4. (define_insn_reservation "cortex_a8_neon_vqneg_vqabs" 4 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vqneg_vqabs")) + (eq_attr "type" "neon_vqneg_vqabs")) "cortex_a8_neon_dp") ;; Instructions using this reservation produce a result at N3. (define_insn_reservation "cortex_a8_neon_vmov" 3 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vmov")) + (eq_attr "type" "neon_vmov")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -247,7 +247,7 @@ (define_insn_reservation "cortex_a8_neon ;; produce a result at N6. (define_insn_reservation "cortex_a8_neon_vaba" 6 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vaba")) + (eq_attr "type" "neon_vaba")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -255,35 +255,35 @@ (define_insn_reservation "cortex_a8_neon ;; produce a result at N6 on cycle 2. (define_insn_reservation "cortex_a8_neon_vaba_qqq" 7 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vaba_qqq")) + (eq_attr "type" "neon_vaba_qqq")) "cortex_a8_neon_dp_2") ;; Instructions using this reservation read their (D|Q)m operands at N1, ;; their (D|Q)d operands at N3, and produce a result at N6. (define_insn_reservation "cortex_a8_neon_vsma" 6 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vsma")) + (eq_attr "type" "neon_vsma")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their source operands at N2, and ;; produce a result at N6. (define_insn_reservation "cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) + (eq_attr "type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their source operands at N2, and ;; produce a result at N6 on cycle 2. (define_insn_reservation "cortex_a8_neon_mul_qqq_8_16_32_ddd_32" 7 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32")) + (eq_attr "type" "neon_mul_qqq_8_16_32_ddd_32")) "cortex_a8_neon_dp_2") ;; Instructions using this reservation read their (D|Q)n operands at N2, ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2. (define_insn_reservation "cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")) + (eq_attr "type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")) "cortex_a8_neon_dp_2") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -291,7 +291,7 @@ (define_insn_reservation "cortex_a8_neon ;; produce a result at N6. (define_insn_reservation "cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")) + (eq_attr "type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -299,7 +299,7 @@ (define_insn_reservation "cortex_a8_neon ;; produce a result at N6 on cycle 2. (define_insn_reservation "cortex_a8_neon_mla_qqq_8_16" 7 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_mla_qqq_8_16")) + (eq_attr "type" "neon_mla_qqq_8_16")) "cortex_a8_neon_dp_2") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -307,7 +307,7 @@ (define_insn_reservation "cortex_a8_neon ;; produce a result at N6 on cycle 2. (define_insn_reservation "cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) + (eq_attr "type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) "cortex_a8_neon_dp_2") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -315,21 +315,21 @@ (define_insn_reservation "cortex_a8_neon ;; produce a result at N6 on cycle 4. (define_insn_reservation "cortex_a8_neon_mla_qqq_32_qqd_32_scalar" 9 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar")) + (eq_attr "type" "neon_mla_qqq_32_qqd_32_scalar")) "cortex_a8_neon_dp_4") ;; Instructions using this reservation read their (D|Q)n operands at N2, ;; their (D|Q)m operands at N1, and produce a result at N6. (define_insn_reservation "cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar" 6 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar")) + (eq_attr "type" "neon_mul_ddd_16_scalar_32_16_long_scalar")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their (D|Q)n operands at N2, ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4. (define_insn_reservation "cortex_a8_neon_mul_qqd_32_scalar" 9 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_mul_qqd_32_scalar")) + (eq_attr "type" "neon_mul_qqd_32_scalar")) "cortex_a8_neon_dp_4") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -337,84 +337,84 @@ (define_insn_reservation "cortex_a8_neon ;; produce a result at N6. (define_insn_reservation "cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) + (eq_attr "type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N3. (define_insn_reservation "cortex_a8_neon_shift_1" 3 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_shift_1")) + (eq_attr "type" "neon_shift_1")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N4. (define_insn_reservation "cortex_a8_neon_shift_2" 4 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_shift_2")) + (eq_attr "type" "neon_shift_2")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N3 on cycle 2. (define_insn_reservation "cortex_a8_neon_shift_3" 4 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_shift_3")) + (eq_attr "type" "neon_shift_3")) "cortex_a8_neon_dp_2") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N1. (define_insn_reservation "cortex_a8_neon_vshl_ddd" 1 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vshl_ddd")) + (eq_attr "type" "neon_vshl_ddd")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N4 on cycle 2. (define_insn_reservation "cortex_a8_neon_vqshl_vrshl_vqrshl_qqq" 5 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq")) + (eq_attr "type" "neon_vqshl_vrshl_vqrshl_qqq")) "cortex_a8_neon_dp_2") ;; Instructions using this reservation read their (D|Q)m operands at N1, ;; their (D|Q)d operands at N3, and produce a result at N6. (define_insn_reservation "cortex_a8_neon_vsra_vrsra" 6 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vsra_vrsra")) + (eq_attr "type" "neon_vsra_vrsra")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their source operands at N2, and ;; produce a result at N5. (define_insn_reservation "cortex_a8_neon_fp_vadd_ddd_vabs_dd" 5 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd")) + (eq_attr "type" "neon_fp_vadd_ddd_vabs_dd")) "cortex_a8_neon_fadd") ;; Instructions using this reservation read their source operands at N2, and ;; produce a result at N5 on cycle 2. (define_insn_reservation "cortex_a8_neon_fp_vadd_qqq_vabs_qq" 6 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq")) + (eq_attr "type" "neon_fp_vadd_qqq_vabs_qq")) "cortex_a8_neon_fadd_2") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N5. (define_insn_reservation "cortex_a8_neon_fp_vsum" 5 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_fp_vsum")) + (eq_attr "type" "neon_fp_vsum")) "cortex_a8_neon_fadd") ;; Instructions using this reservation read their (D|Q)n operands at N2, ;; their (D|Q)m operands at N1, and produce a result at N5. (define_insn_reservation "cortex_a8_neon_fp_vmul_ddd" 5 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_fp_vmul_ddd")) + (eq_attr "type" "neon_fp_vmul_ddd")) "cortex_a8_neon_dp") ;; Instructions using this reservation read their (D|Q)n operands at N2, ;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2. (define_insn_reservation "cortex_a8_neon_fp_vmul_qqd" 6 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_fp_vmul_qqd")) + (eq_attr "type" "neon_fp_vmul_qqd")) "cortex_a8_neon_dp_2") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -422,7 +422,7 @@ (define_insn_reservation "cortex_a8_neon ;; produce a result at N9. (define_insn_reservation "cortex_a8_neon_fp_vmla_ddd" 9 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_fp_vmla_ddd")) + (eq_attr "type" "neon_fp_vmla_ddd")) "cortex_a8_neon_fmul_then_fadd") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -430,7 +430,7 @@ (define_insn_reservation "cortex_a8_neon ;; produce a result at N9 on cycle 2. (define_insn_reservation "cortex_a8_neon_fp_vmla_qqq" 10 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_fp_vmla_qqq")) + (eq_attr "type" "neon_fp_vmla_qqq")) "cortex_a8_neon_fmul_then_fadd_2") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -438,7 +438,7 @@ (define_insn_reservation "cortex_a8_neon ;; produce a result at N9. (define_insn_reservation "cortex_a8_neon_fp_vmla_ddd_scalar" 9 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar")) + (eq_attr "type" "neon_fp_vmla_ddd_scalar")) "cortex_a8_neon_fmul_then_fadd") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -446,152 +446,152 @@ (define_insn_reservation "cortex_a8_neon ;; produce a result at N9 on cycle 2. (define_insn_reservation "cortex_a8_neon_fp_vmla_qqq_scalar" 10 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar")) + (eq_attr "type" "neon_fp_vmla_qqq_scalar")) "cortex_a8_neon_fmul_then_fadd_2") ;; Instructions using this reservation read their source operands at N2, and ;; produce a result at N9. (define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_ddd" 9 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd")) + (eq_attr "type" "neon_fp_vrecps_vrsqrts_ddd")) "cortex_a8_neon_fmul_then_fadd") ;; Instructions using this reservation read their source operands at N2, and ;; produce a result at N9 on cycle 2. (define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_qqq" 10 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq")) + (eq_attr "type" "neon_fp_vrecps_vrsqrts_qqq")) "cortex_a8_neon_fmul_then_fadd_2") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N2. (define_insn_reservation "cortex_a8_neon_bp_simple" 2 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_bp_simple")) + (eq_attr "type" "neon_bp_simple")) "cortex_a8_neon_perm") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N2 on cycle 2. (define_insn_reservation "cortex_a8_neon_bp_2cycle" 3 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_bp_2cycle")) + (eq_attr "type" "neon_bp_2cycle")) "cortex_a8_neon_perm_2") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N2 on cycle 3. (define_insn_reservation "cortex_a8_neon_bp_3cycle" 4 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_bp_3cycle")) + (eq_attr "type" "neon_bp_3cycle")) "cortex_a8_neon_perm_3") ;; Instructions using this reservation produce a result at N1. (define_insn_reservation "cortex_a8_neon_ldr" 1 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_ldr")) + (eq_attr "type" "neon_ldr")) "cortex_a8_neon_ls") ;; Instructions using this reservation read their source operands at N1. (define_insn_reservation "cortex_a8_neon_str" 0 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_str")) + (eq_attr "type" "neon_str")) "cortex_a8_neon_ls") ;; Instructions using this reservation produce a result at N1 on cycle 2. (define_insn_reservation "cortex_a8_neon_vld1_1_2_regs" 2 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vld1_1_2_regs")) + (eq_attr "type" "neon_vld1_1_2_regs")) "cortex_a8_neon_ls_2") ;; Instructions using this reservation produce a result at N1 on cycle 3. (define_insn_reservation "cortex_a8_neon_vld1_3_4_regs" 3 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vld1_3_4_regs")) + (eq_attr "type" "neon_vld1_3_4_regs")) "cortex_a8_neon_ls_3") ;; Instructions using this reservation produce a result at N2 on cycle 2. (define_insn_reservation "cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes" 3 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")) + (eq_attr "type" "neon_vld2_2_regs_vld1_vld2_all_lanes")) "cortex_a8_neon_ls_2") ;; Instructions using this reservation produce a result at N2 on cycle 3. (define_insn_reservation "cortex_a8_neon_vld2_4_regs" 4 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vld2_4_regs")) + (eq_attr "type" "neon_vld2_4_regs")) "cortex_a8_neon_ls_3") ;; Instructions using this reservation produce a result at N2 on cycle 4. (define_insn_reservation "cortex_a8_neon_vld3_vld4" 5 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vld3_vld4")) + (eq_attr "type" "neon_vld3_vld4")) "cortex_a8_neon_ls_4") ;; Instructions using this reservation read their source operands at N1. (define_insn_reservation "cortex_a8_neon_vst1_1_2_regs_vst2_2_regs" 0 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")) + (eq_attr "type" "neon_vst1_1_2_regs_vst2_2_regs")) "cortex_a8_neon_ls_2") ;; Instructions using this reservation read their source operands at N1. (define_insn_reservation "cortex_a8_neon_vst1_3_4_regs" 0 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vst1_3_4_regs")) + (eq_attr "type" "neon_vst1_3_4_regs")) "cortex_a8_neon_ls_3") ;; Instructions using this reservation read their source operands at N1. (define_insn_reservation "cortex_a8_neon_vst2_4_regs_vst3_vst4" 0 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")) + (eq_attr "type" "neon_vst2_4_regs_vst3_vst4")) "cortex_a8_neon_ls_4") ;; Instructions using this reservation read their source operands at N1. (define_insn_reservation "cortex_a8_neon_vst3_vst4" 0 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vst3_vst4")) + (eq_attr "type" "neon_vst3_vst4")) "cortex_a8_neon_ls_4") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N2 on cycle 3. (define_insn_reservation "cortex_a8_neon_vld1_vld2_lane" 4 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vld1_vld2_lane")) + (eq_attr "type" "neon_vld1_vld2_lane")) "cortex_a8_neon_ls_3") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N2 on cycle 5. (define_insn_reservation "cortex_a8_neon_vld3_vld4_lane" 6 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vld3_vld4_lane")) + (eq_attr "type" "neon_vld3_vld4_lane")) "cortex_a8_neon_ls_5") ;; Instructions using this reservation read their source operands at N1. (define_insn_reservation "cortex_a8_neon_vst1_vst2_lane" 0 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vst1_vst2_lane")) + (eq_attr "type" "neon_vst1_vst2_lane")) "cortex_a8_neon_ls_2") ;; Instructions using this reservation read their source operands at N1. (define_insn_reservation "cortex_a8_neon_vst3_vst4_lane" 0 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vst3_vst4_lane")) + (eq_attr "type" "neon_vst3_vst4_lane")) "cortex_a8_neon_ls_3") ;; Instructions using this reservation produce a result at N2 on cycle 2. (define_insn_reservation "cortex_a8_neon_vld3_vld4_all_lanes" 3 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_vld3_vld4_all_lanes")) + (eq_attr "type" "neon_vld3_vld4_all_lanes")) "cortex_a8_neon_ls_3") ;; Instructions using this reservation produce a result at N2. (define_insn_reservation "cortex_a8_neon_mcr" 2 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_mcr")) + (eq_attr "type" "neon_mcr")) "cortex_a8_neon_perm") ;; Instructions using this reservation produce a result at N2. (define_insn_reservation "cortex_a8_neon_mcr_2_mcrr" 2 (and (eq_attr "tune" "cortexa8") - (eq_attr "neon_type" "neon_mcr_2_mcrr")) + (eq_attr "type" "neon_mcr_2_mcrr")) "cortex_a8_neon_perm_2") ;; Exceptions to the default latencies. diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md index 1113a45ff0e499f095adb0f16c3f08a5df4c6a85..acbfef587b0c98a33a089ef70dc77ee1c76d825f 100644 --- a/gcc/config/arm/cortex-a8.md +++ b/gcc/config/arm/cortex-a8.md @@ -85,9 +85,7 @@ (define_reservation "cortex_a8_multiply_ ;; (source read in E2 and destination available at the end of that cycle). (define_insn_reservation "cortex_a8_alu" 2 (and (eq_attr "tune" "cortexa8") - (ior (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg") - (eq_attr "neon_type" "none")) - (eq_attr "type" "clz"))) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,clz")) "cortex_a8_default") (define_insn_reservation "cortex_a8_alu_shift" 2 diff --git a/gcc/config/arm/cortex-a9-neon.md b/gcc/config/arm/cortex-a9-neon.md index 9688edc8f72cffd1a452637313b62d4862664309..2c9d5db5bd8ea4eaf6bcbf49bc04bc955febb21d 100644 --- a/gcc/config/arm/cortex-a9-neon.md +++ b/gcc/config/arm/cortex-a9-neon.md @@ -109,12 +109,12 @@ (define_reservation "cortex_a9_neon_fmul ;; NEON -> core transfers. (define_insn_reservation "ca9_neon_mrc" 1 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_mrc")) + (eq_attr "type" "neon_mrc")) "ca9_issue_vfp_neon + cortex_a9_neon_mcr") (define_insn_reservation "ca9_neon_mrrc" 1 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_mrrc")) + (eq_attr "type" "neon_mrrc")) "ca9_issue_vfp_neon + cortex_a9_neon_mcr") ;; The remainder of this file is auto-generated by neon-schedgen. @@ -123,48 +123,48 @@ (define_insn_reservation "ca9_neon_mrrc" ;; produce a result at N3. (define_insn_reservation "cortex_a9_neon_int_1" 3 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_int_1")) + (eq_attr "type" "neon_int_1")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their (D|Q)m operands at N1, ;; their (D|Q)n operands at N2, and produce a result at N3. (define_insn_reservation "cortex_a9_neon_int_2" 3 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_int_2")) + (eq_attr "type" "neon_int_2")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N3. (define_insn_reservation "cortex_a9_neon_int_3" 3 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_int_3")) + (eq_attr "type" "neon_int_3")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their source operands at N2, and ;; produce a result at N4. (define_insn_reservation "cortex_a9_neon_int_4" 4 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_int_4")) + (eq_attr "type" "neon_int_4")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their (D|Q)m operands at N1, ;; their (D|Q)n operands at N2, and produce a result at N4. (define_insn_reservation "cortex_a9_neon_int_5" 4 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_int_5")) + (eq_attr "type" "neon_int_5")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N4. (define_insn_reservation "cortex_a9_neon_vqneg_vqabs" 4 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vqneg_vqabs")) + (eq_attr "type" "neon_vqneg_vqabs")) "cortex_a9_neon_dp") ;; Instructions using this reservation produce a result at N3. (define_insn_reservation "cortex_a9_neon_vmov" 3 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vmov")) + (eq_attr "type" "neon_vmov")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -172,7 +172,7 @@ (define_insn_reservation "cortex_a9_neon ;; produce a result at N6. (define_insn_reservation "cortex_a9_neon_vaba" 6 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vaba")) + (eq_attr "type" "neon_vaba")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -180,35 +180,35 @@ (define_insn_reservation "cortex_a9_neon ;; produce a result at N6 on cycle 2. (define_insn_reservation "cortex_a9_neon_vaba_qqq" 7 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vaba_qqq")) + (eq_attr "type" "neon_vaba_qqq")) "cortex_a9_neon_dp_2") ;; Instructions using this reservation read their (D|Q)m operands at N1, ;; their (D|Q)d operands at N3, and produce a result at N6. (define_insn_reservation "cortex_a9_neon_vsma" 6 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vsma")) + (eq_attr "type" "neon_vsma")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their source operands at N2, and ;; produce a result at N6. (define_insn_reservation "cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) + (eq_attr "type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their source operands at N2, and ;; produce a result at N6 on cycle 2. (define_insn_reservation "cortex_a9_neon_mul_qqq_8_16_32_ddd_32" 7 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32")) + (eq_attr "type" "neon_mul_qqq_8_16_32_ddd_32")) "cortex_a9_neon_dp_2") ;; Instructions using this reservation read their (D|Q)n operands at N2, ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2. (define_insn_reservation "cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")) + (eq_attr "type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")) "cortex_a9_neon_dp_2") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -216,7 +216,7 @@ (define_insn_reservation "cortex_a9_neon ;; produce a result at N6. (define_insn_reservation "cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")) + (eq_attr "type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -224,7 +224,7 @@ (define_insn_reservation "cortex_a9_neon ;; produce a result at N6 on cycle 2. (define_insn_reservation "cortex_a9_neon_mla_qqq_8_16" 7 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_mla_qqq_8_16")) + (eq_attr "type" "neon_mla_qqq_8_16")) "cortex_a9_neon_dp_2") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -232,7 +232,7 @@ (define_insn_reservation "cortex_a9_neon ;; produce a result at N6 on cycle 2. (define_insn_reservation "cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) + (eq_attr "type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) "cortex_a9_neon_dp_2") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -240,21 +240,21 @@ (define_insn_reservation "cortex_a9_neon ;; produce a result at N6 on cycle 4. (define_insn_reservation "cortex_a9_neon_mla_qqq_32_qqd_32_scalar" 9 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar")) + (eq_attr "type" "neon_mla_qqq_32_qqd_32_scalar")) "cortex_a9_neon_dp_4") ;; Instructions using this reservation read their (D|Q)n operands at N2, ;; their (D|Q)m operands at N1, and produce a result at N6. (define_insn_reservation "cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar" 6 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar")) + (eq_attr "type" "neon_mul_ddd_16_scalar_32_16_long_scalar")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their (D|Q)n operands at N2, ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4. (define_insn_reservation "cortex_a9_neon_mul_qqd_32_scalar" 9 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_mul_qqd_32_scalar")) + (eq_attr "type" "neon_mul_qqd_32_scalar")) "cortex_a9_neon_dp_4") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -262,84 +262,84 @@ (define_insn_reservation "cortex_a9_neon ;; produce a result at N6. (define_insn_reservation "cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) + (eq_attr "type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N3. (define_insn_reservation "cortex_a9_neon_shift_1" 3 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_shift_1")) + (eq_attr "type" "neon_shift_1")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N4. (define_insn_reservation "cortex_a9_neon_shift_2" 4 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_shift_2")) + (eq_attr "type" "neon_shift_2")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N3 on cycle 2. (define_insn_reservation "cortex_a9_neon_shift_3" 4 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_shift_3")) + (eq_attr "type" "neon_shift_3")) "cortex_a9_neon_dp_2") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N1. (define_insn_reservation "cortex_a9_neon_vshl_ddd" 1 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vshl_ddd")) + (eq_attr "type" "neon_vshl_ddd")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N4 on cycle 2. (define_insn_reservation "cortex_a9_neon_vqshl_vrshl_vqrshl_qqq" 5 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq")) + (eq_attr "type" "neon_vqshl_vrshl_vqrshl_qqq")) "cortex_a9_neon_dp_2") ;; Instructions using this reservation read their (D|Q)m operands at N1, ;; their (D|Q)d operands at N3, and produce a result at N6. (define_insn_reservation "cortex_a9_neon_vsra_vrsra" 6 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vsra_vrsra")) + (eq_attr "type" "neon_vsra_vrsra")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their source operands at N2, and ;; produce a result at N5. (define_insn_reservation "cortex_a9_neon_fp_vadd_ddd_vabs_dd" 5 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd")) + (eq_attr "type" "neon_fp_vadd_ddd_vabs_dd")) "cortex_a9_neon_fadd") ;; Instructions using this reservation read their source operands at N2, and ;; produce a result at N5 on cycle 2. (define_insn_reservation "cortex_a9_neon_fp_vadd_qqq_vabs_qq" 6 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq")) + (eq_attr "type" "neon_fp_vadd_qqq_vabs_qq")) "cortex_a9_neon_fadd_2") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N5. (define_insn_reservation "cortex_a9_neon_fp_vsum" 5 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_fp_vsum")) + (eq_attr "type" "neon_fp_vsum")) "cortex_a9_neon_fadd") ;; Instructions using this reservation read their (D|Q)n operands at N2, ;; their (D|Q)m operands at N1, and produce a result at N5. (define_insn_reservation "cortex_a9_neon_fp_vmul_ddd" 5 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_fp_vmul_ddd")) + (eq_attr "type" "neon_fp_vmul_ddd")) "cortex_a9_neon_dp") ;; Instructions using this reservation read their (D|Q)n operands at N2, ;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2. (define_insn_reservation "cortex_a9_neon_fp_vmul_qqd" 6 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_fp_vmul_qqd")) + (eq_attr "type" "neon_fp_vmul_qqd")) "cortex_a9_neon_dp_2") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -347,7 +347,7 @@ (define_insn_reservation "cortex_a9_neon ;; produce a result at N9. (define_insn_reservation "cortex_a9_neon_fp_vmla_ddd" 9 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_fp_vmla_ddd")) + (eq_attr "type" "neon_fp_vmla_ddd")) "cortex_a9_neon_fmul_then_fadd") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -355,7 +355,7 @@ (define_insn_reservation "cortex_a9_neon ;; produce a result at N9 on cycle 2. (define_insn_reservation "cortex_a9_neon_fp_vmla_qqq" 10 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_fp_vmla_qqq")) + (eq_attr "type" "neon_fp_vmla_qqq")) "cortex_a9_neon_fmul_then_fadd_2") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -363,7 +363,7 @@ (define_insn_reservation "cortex_a9_neon ;; produce a result at N9. (define_insn_reservation "cortex_a9_neon_fp_vmla_ddd_scalar" 9 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar")) + (eq_attr "type" "neon_fp_vmla_ddd_scalar")) "cortex_a9_neon_fmul_then_fadd") ;; Instructions using this reservation read their (D|Q)n operands at N2, @@ -371,152 +371,152 @@ (define_insn_reservation "cortex_a9_neon ;; produce a result at N9 on cycle 2. (define_insn_reservation "cortex_a9_neon_fp_vmla_qqq_scalar" 10 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar")) + (eq_attr "type" "neon_fp_vmla_qqq_scalar")) "cortex_a9_neon_fmul_then_fadd_2") ;; Instructions using this reservation read their source operands at N2, and ;; produce a result at N9. (define_insn_reservation "cortex_a9_neon_fp_vrecps_vrsqrts_ddd" 9 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd")) + (eq_attr "type" "neon_fp_vrecps_vrsqrts_ddd")) "cortex_a9_neon_fmul_then_fadd") ;; Instructions using this reservation read their source operands at N2, and ;; produce a result at N9 on cycle 2. (define_insn_reservation "cortex_a9_neon_fp_vrecps_vrsqrts_qqq" 10 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq")) + (eq_attr "type" "neon_fp_vrecps_vrsqrts_qqq")) "cortex_a9_neon_fmul_then_fadd_2") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N2. (define_insn_reservation "cortex_a9_neon_bp_simple" 2 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_bp_simple")) + (eq_attr "type" "neon_bp_simple")) "cortex_a9_neon_perm") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N2 on cycle 2. (define_insn_reservation "cortex_a9_neon_bp_2cycle" 3 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_bp_2cycle")) + (eq_attr "type" "neon_bp_2cycle")) "cortex_a9_neon_perm_2") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N2 on cycle 3. (define_insn_reservation "cortex_a9_neon_bp_3cycle" 4 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_bp_3cycle")) + (eq_attr "type" "neon_bp_3cycle")) "cortex_a9_neon_perm_3") ;; Instructions using this reservation produce a result at N1. (define_insn_reservation "cortex_a9_neon_ldr" 1 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_ldr")) + (eq_attr "type" "neon_ldr")) "cortex_a9_neon_ls") ;; Instructions using this reservation read their source operands at N1. (define_insn_reservation "cortex_a9_neon_str" 0 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_str")) + (eq_attr "type" "neon_str")) "cortex_a9_neon_ls") ;; Instructions using this reservation produce a result at N1 on cycle 2. (define_insn_reservation "cortex_a9_neon_vld1_1_2_regs" 2 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vld1_1_2_regs")) + (eq_attr "type" "neon_vld1_1_2_regs")) "cortex_a9_neon_ls_2") ;; Instructions using this reservation produce a result at N1 on cycle 3. (define_insn_reservation "cortex_a9_neon_vld1_3_4_regs" 3 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vld1_3_4_regs")) + (eq_attr "type" "neon_vld1_3_4_regs")) "cortex_a9_neon_ls_3") ;; Instructions using this reservation produce a result at N2 on cycle 2. (define_insn_reservation "cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes" 3 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")) + (eq_attr "type" "neon_vld2_2_regs_vld1_vld2_all_lanes")) "cortex_a9_neon_ls_2") ;; Instructions using this reservation produce a result at N2 on cycle 3. (define_insn_reservation "cortex_a9_neon_vld2_4_regs" 4 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vld2_4_regs")) + (eq_attr "type" "neon_vld2_4_regs")) "cortex_a9_neon_ls_3") ;; Instructions using this reservation produce a result at N2 on cycle 4. (define_insn_reservation "cortex_a9_neon_vld3_vld4" 5 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vld3_vld4")) + (eq_attr "type" "neon_vld3_vld4")) "cortex_a9_neon_ls_4") ;; Instructions using this reservation read their source operands at N1. (define_insn_reservation "cortex_a9_neon_vst1_1_2_regs_vst2_2_regs" 0 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")) + (eq_attr "type" "neon_vst1_1_2_regs_vst2_2_regs")) "cortex_a9_neon_ls_2") ;; Instructions using this reservation read their source operands at N1. (define_insn_reservation "cortex_a9_neon_vst1_3_4_regs" 0 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vst1_3_4_regs")) + (eq_attr "type" "neon_vst1_3_4_regs")) "cortex_a9_neon_ls_3") ;; Instructions using this reservation read their source operands at N1. (define_insn_reservation "cortex_a9_neon_vst2_4_regs_vst3_vst4" 0 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")) + (eq_attr "type" "neon_vst2_4_regs_vst3_vst4")) "cortex_a9_neon_ls_4") ;; Instructions using this reservation read their source operands at N1. (define_insn_reservation "cortex_a9_neon_vst3_vst4" 0 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vst3_vst4")) + (eq_attr "type" "neon_vst3_vst4")) "cortex_a9_neon_ls_4") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N2 on cycle 3. (define_insn_reservation "cortex_a9_neon_vld1_vld2_lane" 4 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vld1_vld2_lane")) + (eq_attr "type" "neon_vld1_vld2_lane")) "cortex_a9_neon_ls_3") ;; Instructions using this reservation read their source operands at N1, and ;; produce a result at N2 on cycle 5. (define_insn_reservation "cortex_a9_neon_vld3_vld4_lane" 6 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vld3_vld4_lane")) + (eq_attr "type" "neon_vld3_vld4_lane")) "cortex_a9_neon_ls_5") ;; Instructions using this reservation read their source operands at N1. (define_insn_reservation "cortex_a9_neon_vst1_vst2_lane" 0 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vst1_vst2_lane")) + (eq_attr "type" "neon_vst1_vst2_lane")) "cortex_a9_neon_ls_2") ;; Instructions using this reservation read their source operands at N1. (define_insn_reservation "cortex_a9_neon_vst3_vst4_lane" 0 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vst3_vst4_lane")) + (eq_attr "type" "neon_vst3_vst4_lane")) "cortex_a9_neon_ls_3") ;; Instructions using this reservation produce a result at N2 on cycle 2. (define_insn_reservation "cortex_a9_neon_vld3_vld4_all_lanes" 3 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_vld3_vld4_all_lanes")) + (eq_attr "type" "neon_vld3_vld4_all_lanes")) "cortex_a9_neon_ls_3") ;; Instructions using this reservation produce a result at N2. (define_insn_reservation "cortex_a9_neon_mcr" 2 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_mcr")) + (eq_attr "type" "neon_mcr")) "cortex_a9_neon_perm") ;; Instructions using this reservation produce a result at N2. (define_insn_reservation "cortex_a9_neon_mcr_2_mcrr" 2 (and (eq_attr "tune" "cortexa9") - (eq_attr "neon_type" "neon_mcr_2_mcrr")) + (eq_attr "type" "neon_mcr_2_mcrr")) "cortex_a9_neon_perm_2") ;; Exceptions to the default latencies. diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md index 11dc0b32c38b250bd6bba4b5e390403c3de3812e..198e8de80cfe46dff253bf720812b41bb1446c54 100644 --- a/gcc/config/arm/cortex-a9.md +++ b/gcc/config/arm/cortex-a9.md @@ -80,10 +80,9 @@ (define_reservation "cortex_a9_mult_long ;; which can go down E2 without any problem. (define_insn_reservation "cortex_a9_dp" 2 (and (eq_attr "tune" "cortexa9") - (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ - mov_imm,mov_reg,mvn_imm,mvn_reg,\ - mov_shift_reg,mov_shift") - (eq_attr "neon_type" "none"))) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ + mov_imm,mov_reg,mvn_imm,mvn_reg,\ + mov_shift_reg,mov_shift")) "cortex_a9_p0_default|cortex_a9_p1_default") ;; An instruction using the shifter will go down E1. @@ -200,7 +199,7 @@ (define_insn_reservation "cortex_a9_call ;; Pipelining for VFP instructions. ;; Issue happens either along load store unit or the VFP / Neon unit. ;; Pipeline Instruction Classification. -;; FPS - fcpys, ffariths, ffarithd,r_2_f,f_2_r +;; FPS - fcpys, ffariths, ffarithd,f_mcr,f_mcrr,f_mrc,f_mrrc ;; FP_ADD - fadds, faddd, fcmps (1) ;; FPMUL - fmul{s,d}, fmac{s,d}, ffma{s,d} ;; FPDIV - fdiv{s,d} @@ -213,7 +212,8 @@ (define_cpu_unit "ca9fp_ds1" "cortex_a9" ;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle. (define_insn_reservation "cortex_a9_fps" 2 (and (eq_attr "tune" "cortexa9") - (eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd, r_2_f, f_2_r, f_flag")) + (eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd,\ + f_mcr, f_mcrr, f_mrc, f_mrrc, f_flag")) "ca9_issue_vfp_neon + ca9fps") (define_bypass 1 diff --git a/gcc/config/arm/cortex-m4-fpu.md b/gcc/config/arm/cortex-m4-fpu.md index 4ce3f10f0debac5d9888e56d757986f60d947a73..f148e9dba798177a105df6a36e188d3dff7b890e 100644 --- a/gcc/config/arm/cortex-m4-fpu.md +++ b/gcc/config/arm/cortex-m4-fpu.md @@ -40,7 +40,7 @@ (define_insn_reservation "cortex_m4_vmov (define_insn_reservation "cortex_m4_vmov_2" 2 (and (eq_attr "tune" "cortexm4") - (eq_attr "type" "f_2_r,r_2_f")) + (eq_attr "type" "f_mrc,f_mrrc,f_mcr,f_mcrr")) "cortex_m4_ex_v*2") (define_insn_reservation "cortex_m4_fmuls" 2 diff --git a/gcc/config/arm/cortex-r4f.md b/gcc/config/arm/cortex-r4f.md index 0c0bae0cd7400a2496cac2052470309d6a77a13b..8262ccd5b659a64c2dcf7b02e277188657c5164e 100644 --- a/gcc/config/arm/cortex-r4f.md +++ b/gcc/config/arm/cortex-r4f.md @@ -83,12 +83,12 @@ (define_insn_reservation "cortex_r4_fsto (define_insn_reservation "cortex_r4_mcr" 2 (and (eq_attr "tune_cortexr4" "yes") - (eq_attr "type" "r_2_f")) + (eq_attr "type" "f_mcr,f_mcrr")) "cortex_r4_issue_ab") (define_insn_reservation "cortex_r4_mrc" 3 (and (eq_attr "tune_cortexr4" "yes") - (eq_attr "type" "f_2_r")) + (eq_attr "type" "f_mrc,f_mrrc")) "cortex_r4_issue_ab") ;; Bypasses for normal (not early) regs. diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index d84929f3d1fb9836207b1f79c6f0ddcb39055c07..c7d7079b9de69d42d2659864f90dd50f1c6add72 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -391,7 +391,7 @@ (define_mode_attr V_suf64 [(V8QI "") (V1 (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t") (V8HI "x") (V4SI "t") (V4SF "t")]) -;; Predicates used for setting neon_type +;; Predicates used for setting type for neon instructions (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false") (V4HI "false") (V8HI "false") diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md index f1f0a5c515066ebefb04fbfc6f01c1774c5a3a13..3966715d4732b1e20fe6ddfbc4071e415292c410 100644 --- a/gcc/config/arm/iwmmxt.md +++ b/gcc/config/arm/iwmmxt.md @@ -155,7 +155,8 @@ (define_insn "*iwmmxt_arm_movdi" (const_int 8) (const_int 4))] (const_int 4))) - (set_attr "type" "*,*,*,load2,store2,wmmx_wmov,wmmx_tmcrr,wmmx_tmrrc,wmmx_wldr,wmmx_wstr,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") + (set_attr "type" "*,*,*,load2,store2,*,*,*,*,*,f_mcrr,f_mrrc,\ + ffarithd,f_loadd,f_stored") (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,1020,*") (set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*")] ) @@ -187,7 +188,8 @@ (define_insn "*iwmmxt_movsi_insn" default: gcc_unreachable (); }" - [(set_attr "type" "*,*,*,*,load1,store1,wmmx_tmcr,wmmx_tmrc,wmmx_wldr,wmmx_wstr,r_2_f,f_2_r,fcpys,f_loads,f_stores") + [(set_attr "type" "*,*,*,*,load1,store1,*,*,*,*,f_mcr,f_mrc,\ + fcpys,f_loads,f_stores") (set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*") (set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024, *,*,*,*,1020,*") (set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *, 1012,*,*,*,1008,*") diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md index 0e2c443721e5bff7fc50b46177b0b288c8bf90d9..3d1bf596f86cff31f3b24f3df587095e0963a400 100644 --- a/gcc/config/arm/marvell-pj4.md +++ b/gcc/config/arm/marvell-pj4.md @@ -201,9 +201,9 @@ (define_insn_reservation "pj4_vfp_store" (define_insn_reservation "pj4_vfp_to_core" 7 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "f_2_r,f_flag")) "pj4_isb,nothing,nothing,vissue,vfast,nothing*2") + (eq_attr "type" "f_mrc,f_mrrc,f_flag")) "pj4_isb,nothing,nothing,vissue,vfast,nothing*2") (define_insn_reservation "pj4_core_to_vfp" 2 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "r_2_f")) "pj4_isb,pj4_alu1,pj4_w1,vissue,pj4_cp") + (eq_attr "type" "f_mcr,f_mcrr")) "pj4_isb,pj4_alu1,pj4_w1,vissue,pj4_cp") diff --git a/gcc/config/arm/neon-schedgen.ml b/gcc/config/arm/neon-schedgen.ml index 7dacbab..b369956 100644 --- a/gcc/config/arm/neon-schedgen.ml +++ b/gcc/config/arm/neon-schedgen.ml @@ -480,7 +480,7 @@ let emit_insn_reservations core = Printf.printf "(define_insn_reservation \"%s_%s\" %d\n" corestring producer latency; Printf.printf " (and (eq_attr \"tune\" \"%s\")\n" tunestring; - Printf.printf " (eq_attr \"neon_type\" \"%s\"))\n" producer; + Printf.printf " (eq_attr \"type\" \"%s\"))\n" producer; let str = match reservation with Mul -> "dp" | Mul_2cycle -> "dp_2" | Mul_4cycle -> "dp_4" diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index e00ca2c7bf982f71c377dec73ee438687aadad02..ae83dba5f895276800a0973498530e1c0c8d1196 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -20,7 +20,7 @@ ;; Attribute used to permit string comparisons against in -;; neon_type attribute definitions. +;; type attribute definitions. (define_attr "vqh_mnem" "vadd,vmin,vmax" (const_string "vadd")) (define_insn "*neon_mov" @@ -60,8 +60,8 @@ (define_insn "*neon_mov" default: return output_move_double (operands, true, NULL); } } - [(set_attr "neon_type" "neon_int_1,*,neon_vmov,*,neon_mrrc,neon_mcr_2_mcrr,*,*,*") - (set_attr "type" "*,f_stored,*,f_loadd,*,*,mov_reg,load2,store2") + [(set_attr "type" "neon_int_1,f_stored,neon_vmov,f_loadd,neon_mrrc,\ + neon_mcr_2_mcrr,mov_reg,load2,store2") (set_attr "length" "4,4,4,4,4,4,8,8,8") (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*") (set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*") @@ -104,9 +104,8 @@ (define_insn "*neon_mov" default: return output_move_quad (operands); } } - [(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\ - neon_mrrc,neon_mcr_2_mcrr,*,*,*") - (set_attr "type" "*,*,*,*,*,*,mov_reg,load4,store4") + [(set_attr "type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\ + neon_mrrc,neon_mcr_2_mcrr,mov_reg,load4,store4") (set_attr "length" "4,8,4,8,8,8,16,8,16") (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*") (set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*") @@ -150,7 +149,7 @@ (define_insn "*neon_mov" default: gcc_unreachable (); } } - [(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_ldm_2") + [(set_attr "type" "neon_int_1,neon_stm_2,neon_ldm_2") (set (attr "length") (symbol_ref "arm_attr_length_move_neon (insn)"))]) (define_split @@ -258,7 +257,7 @@ (define_insn "*movmisalign_neon_st UNSPEC_MISALIGNED_ACCESS))] "TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access" "vst1.\t{%P1}, %A0" - [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) + [(set_attr "type" "neon_vst1_1_2_regs_vst2_2_regs")]) (define_insn "*movmisalign_neon_load" [(set (match_operand:VDX 0 "s_register_operand" "=w") @@ -267,7 +266,7 @@ (define_insn "*movmisalign_neon_lo UNSPEC_MISALIGNED_ACCESS))] "TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access" "vld1.\t{%P0}, %A1" - [(set_attr "neon_type" "neon_vld1_1_2_regs")]) + [(set_attr "type" "neon_vld1_1_2_regs")]) (define_insn "*movmisalign_neon_store" [(set (match_operand:VQX 0 "neon_permissive_struct_operand" "=Um") @@ -275,7 +274,7 @@ (define_insn "*movmisalign_neon_st UNSPEC_MISALIGNED_ACCESS))] "TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access" "vst1.\t{%q1}, %A0" - [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) + [(set_attr "type" "neon_vst1_1_2_regs_vst2_2_regs")]) (define_insn "*movmisalign_neon_load" [(set (match_operand:VQX 0 "s_register_operand" "=w") @@ -284,7 +283,7 @@ (define_insn "*movmisalign_neon_lo UNSPEC_MISALIGNED_ACCESS))] "TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access" "vld1.\t{%q0}, %A1" - [(set_attr "neon_type" "neon_vld1_1_2_regs")]) + [(set_attr "type" "neon_vld1_1_2_regs")]) (define_insn "vec_set_internal" [(set (match_operand:VD 0 "s_register_operand" "=w,w") @@ -305,7 +304,7 @@ (define_insn "vec_set_internal" else return "vmov.\t%P0[%c2], %1"; } - [(set_attr "neon_type" "neon_vld1_vld2_lane,neon_mcr")]) + [(set_attr "type" "neon_vld1_vld2_lane,neon_mcr")]) (define_insn "vec_set_internal" [(set (match_operand:VQ 0 "s_register_operand" "=w,w") @@ -333,7 +332,7 @@ (define_insn "vec_set_internal" else return "vmov.\t%P0[%c2], %1"; } - [(set_attr "neon_type" "neon_vld1_vld2_lane,neon_mcr")] + [(set_attr "type" "neon_vld1_vld2_lane,neon_mcr")] ) (define_insn "vec_setv2di_internal" @@ -355,7 +354,7 @@ (define_insn "vec_setv2di_internal" else return "vmov\t%P0, %Q1, %R1"; } - [(set_attr "neon_type" "neon_vld1_1_2_regs,neon_mcr_2_mcrr")] + [(set_attr "type" "neon_vld1_1_2_regs,neon_mcr_2_mcrr")] ) (define_expand "vec_set" @@ -389,7 +388,7 @@ (define_insn "vec_extract" else return "vmov.\t%0, %P1[%c2]"; } - [(set_attr "neon_type" "neon_vst1_vst2_lane,neon_bp_simple")] + [(set_attr "type" "neon_vst1_vst2_lane,neon_bp_simple")] ) (define_insn "vec_extract" @@ -415,7 +414,7 @@ (define_insn "vec_extract" else return "vmov.\t%0, %P1[%c2]"; } - [(set_attr "neon_type" "neon_vst1_vst2_lane,neon_bp_simple")] + [(set_attr "type" "neon_vst1_vst2_lane,neon_bp_simple")] ) (define_insn "vec_extractv2di" @@ -434,7 +433,7 @@ (define_insn "vec_extractv2di" else return "vmov\t%Q0, %R0, %P1 @ v2di"; } - [(set_attr "neon_type" "neon_vst1_vst2_lane,neon_int_1")] + [(set_attr "type" "neon_vst1_vst2_lane,neon_int_1")] ) (define_expand "vec_init" @@ -457,7 +456,7 @@ (define_insn "*add3_neon" (match_operand:VDQ 2 "s_register_operand" "w")))] "TARGET_NEON && (! || flag_unsafe_math_optimizations)" "vadd.\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -484,7 +483,7 @@ (define_insn "adddi3_neon" default: gcc_unreachable (); } } - [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1,*,*,*") + [(set_attr "type" "neon_int_1,*,*,neon_int_1,*,*,*") (set_attr "conds" "*,clob,clob,*,clob,clob,clob") (set_attr "length" "*,8,8,*,8,8,8") (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits,*,*,*")] @@ -496,7 +495,7 @@ (define_insn "*sub3_neon" (match_operand:VDQ 2 "s_register_operand" "w")))] "TARGET_NEON && (! || flag_unsafe_math_optimizations)" "vsub.\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -521,7 +520,7 @@ (define_insn "subdi3_neon" default: gcc_unreachable (); } } - [(set_attr "neon_type" "neon_int_2,*,*,*,neon_int_2") + [(set_attr "type" "neon_int_2,*,*,*,neon_int_2") (set_attr "conds" "*,clob,clob,clob,*") (set_attr "length" "*,8,8,8,*") (set_attr "arch" "neon_for_64bits,*,*,*,avoid_neon_for_64bits")] @@ -533,7 +532,7 @@ (define_insn "*mul3_neon" (match_operand:VDQ 2 "s_register_operand" "w")))] "TARGET_NEON && (! || flag_unsafe_math_optimizations)" "vmul.\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -555,7 +554,7 @@ (define_insn "mul3add_neon" (match_operand:VDQ 1 "s_register_operand" "0")))] "TARGET_NEON && (! || flag_unsafe_math_optimizations)" "vmla.\t%0, %2, %3" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vmla_ddd") @@ -577,7 +576,7 @@ (define_insn "mul3negadd || flag_unsafe_math_optimizations)" "vmls.\t%0, %2, %3" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vmla_ddd") @@ -604,7 +603,7 @@ (define_insn "fma4" (match_operand:VCVTF 3 "register_operand" "0")))] "TARGET_NEON && TARGET_FMA && flag_unsafe_math_optimizations" "vfma%?.\\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vmla_ddd") (const_string "neon_fp_vmla_qqq")))] @@ -617,7 +616,7 @@ (define_insn "fma4_intrinsic (match_operand:VCVTF 3 "register_operand" "0")))] "TARGET_NEON && TARGET_FMA" "vfma%?.\\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vmla_ddd") (const_string "neon_fp_vmla_qqq")))] @@ -630,7 +629,7 @@ (define_insn "*fmsub4" (match_operand:VCVTF 3 "register_operand" "0")))] "TARGET_NEON && TARGET_FMA && flag_unsafe_math_optimizations" "vfms%?.\\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vmla_ddd") (const_string "neon_fp_vmla_qqq")))] @@ -643,7 +642,7 @@ (define_insn "fmsub4_intrins (match_operand:VCVTF 3 "register_operand" "0")))] "TARGET_NEON && TARGET_FMA" "vfms%?.\\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vmla_ddd") (const_string "neon_fp_vmla_qqq")))] @@ -656,7 +655,7 @@ (define_insn "neon_vrint%?.f32\\t%0, %1" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_fp_vadd_qqq_vabs_qq")))] @@ -676,7 +675,7 @@ (define_insn "ior3" default: gcc_unreachable (); } } - [(set_attr "neon_type" "neon_int_1")] + [(set_attr "type" "neon_int_1")] ) ;; The concrete forms of the Neon immediate-logic instructions are vbic and @@ -698,7 +697,7 @@ (define_insn "and3" default: gcc_unreachable (); } } - [(set_attr "neon_type" "neon_int_1")] + [(set_attr "type" "neon_int_1")] ) (define_insn "orn3_neon" @@ -707,7 +706,7 @@ (define_insn "orn3_neon" (match_operand:VDQ 1 "s_register_operand" "w")))] "TARGET_NEON" "vorn\t%0, %1, %2" - [(set_attr "neon_type" "neon_int_1")] + [(set_attr "type" "neon_int_1")] ) ;; TODO: investigate whether we should disable @@ -745,7 +744,7 @@ (define_insn_and_split "orndi3_neon" DONE; } }" - [(set_attr "neon_type" "neon_int_1,*,*,*") + [(set_attr "type" "neon_int_1,*,*,*") (set_attr "length" "*,16,8,8") (set_attr "arch" "any,a,t2,t2")] ) @@ -756,7 +755,7 @@ (define_insn "bic3_neon" (match_operand:VDQ 1 "s_register_operand" "w")))] "TARGET_NEON" "vbic\t%0, %1, %2" - [(set_attr "neon_type" "neon_int_1")] + [(set_attr "type" "neon_int_1")] ) ;; Compare to *anddi_notdi_di. @@ -769,7 +768,7 @@ (define_insn "bicdi3_neon" vbic\t%P0, %P1, %P2 # #" - [(set_attr "neon_type" "neon_int_1,*,*") + [(set_attr "type" "neon_int_1,*,*") (set_attr "length" "*,8,8")] ) @@ -779,7 +778,7 @@ (define_insn "xor3" (match_operand:VDQ 2 "s_register_operand" "w")))] "TARGET_NEON" "veor\t%0, %1, %2" - [(set_attr "neon_type" "neon_int_1")] + [(set_attr "type" "neon_int_1")] ) (define_insn "one_cmpl2" @@ -787,7 +786,7 @@ (define_insn "one_cmpl2" (not:VDQ (match_operand:VDQ 1 "s_register_operand" "w")))] "TARGET_NEON" "vmvn\t%0, %1" - [(set_attr "neon_type" "neon_int_1")] + [(set_attr "type" "neon_int_1")] ) (define_insn "abs2" @@ -795,7 +794,7 @@ (define_insn "abs2" (abs:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))] "TARGET_NEON" "vabs.\t%0, %1" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -808,7 +807,7 @@ (define_insn "neg2" (neg:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))] "TARGET_NEON" "vneg.\t%0, %1" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -861,7 +860,7 @@ (define_insn "*umin3_neon" (match_operand:VDQIW 2 "s_register_operand" "w")))] "TARGET_NEON" "vmin.\t%0, %1, %2" - [(set_attr "neon_type" "neon_int_5")] + [(set_attr "type" "neon_int_5")] ) (define_insn "*umax3_neon" @@ -870,7 +869,7 @@ (define_insn "*umax3_neon" (match_operand:VDQIW 2 "s_register_operand" "w")))] "TARGET_NEON" "vmax.\t%0, %1, %2" - [(set_attr "neon_type" "neon_int_5")] + [(set_attr "type" "neon_int_5")] ) (define_insn "*smin3_neon" @@ -879,7 +878,7 @@ (define_insn "*smin3_neon" (match_operand:VDQW 2 "s_register_operand" "w")))] "TARGET_NEON" "vmin.\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_int_5")))] @@ -891,7 +890,7 @@ (define_insn "*smax3_neon" (match_operand:VDQW 2 "s_register_operand" "w")))] "TARGET_NEON" "vmax.\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_int_5")))] @@ -917,7 +916,7 @@ (define_insn "vashl3" default: gcc_unreachable (); } } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_vshl_ddd") (const_string "neon_shift_3")))] @@ -933,7 +932,7 @@ (define_insn "vashr3_imm" mode, VALID_NEON_QREG_MODE (mode), false); } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_vshl_ddd") (const_string "neon_shift_3")))] @@ -949,7 +948,7 @@ (define_insn "vlshr3_imm" mode, VALID_NEON_QREG_MODE (mode), false); } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_vshl_ddd") (const_string "neon_shift_3")))] @@ -967,7 +966,7 @@ (define_insn "ashl3_signed" UNSPEC_ASHIFT_SIGNED))] "TARGET_NEON" "vshl.\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_vshl_ddd") (const_string "neon_shift_3")))] @@ -983,7 +982,7 @@ (define_insn "ashl3_unsigned" UNSPEC_ASHIFT_UNSIGNED))] "TARGET_NEON" "vshl.\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_vshl_ddd") (const_string "neon_shift_3")))] @@ -1038,7 +1037,7 @@ (define_insn "neon_load_count" "@ vld1.32\t{%P0[0]}, %A1 vmov.32\t%P0[0], %1" - [(set_attr "neon_type" "neon_vld1_vld2_lane,neon_mcr")] + [(set_attr "type" "neon_vld1_vld2_lane,neon_mcr")] ) (define_insn "ashldi3_neon_noclobber" @@ -1051,7 +1050,7 @@ (define_insn "ashldi3_neon_noclobber" "@ vshl.u64\t%P0, %P1, %2 vshl.u64\t%P0, %P1, %P2" - [(set_attr "neon_type" "neon_vshl_ddd,neon_vshl_ddd")] + [(set_attr "type" "neon_vshl_ddd,neon_vshl_ddd")] ) (define_insn_and_split "ashldi3_neon" @@ -1113,7 +1112,7 @@ (define_insn "signed_shift_di3_neon" UNSPEC_ASHIFT_SIGNED))] "TARGET_NEON && reload_completed" "vshl.s64\t%P0, %P1, %P2" - [(set_attr "neon_type" "neon_vshl_ddd")] + [(set_attr "type" "neon_vshl_ddd")] ) ; The shift amount needs to be negated for right-shifts @@ -1124,7 +1123,7 @@ (define_insn "unsigned_shift_di3_neon" UNSPEC_ASHIFT_UNSIGNED))] "TARGET_NEON && reload_completed" "vshl.u64\t%P0, %P1, %P2" - [(set_attr "neon_type" "neon_vshl_ddd")] + [(set_attr "type" "neon_vshl_ddd")] ) (define_insn "ashrdi3_neon_imm_noclobber" @@ -1134,7 +1133,7 @@ (define_insn "ashrdi3_neon_imm_noclobber "TARGET_NEON && reload_completed && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 64" "vshr.s64\t%P0, %P1, %2" - [(set_attr "neon_type" "neon_vshl_ddd")] + [(set_attr "type" "neon_vshl_ddd")] ) (define_insn "lshrdi3_neon_imm_noclobber" @@ -1144,7 +1143,7 @@ (define_insn "lshrdi3_neon_imm_noclobber "TARGET_NEON && reload_completed && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 64" "vshr.u64\t%P0, %P1, %2" - [(set_attr "neon_type" "neon_vshl_ddd")] + [(set_attr "type" "neon_vshl_ddd")] ) ;; ashrdi3_neon @@ -1215,7 +1214,7 @@ (define_insn "widen_ssum3" (match_operand: 2 "s_register_operand" "w")))] "TARGET_NEON" "vaddw.\t%q0, %q2, %P1" - [(set_attr "neon_type" "neon_int_3")] + [(set_attr "type" "neon_int_3")] ) (define_insn "widen_usum3" @@ -1225,7 +1224,7 @@ (define_insn "widen_usum3" (match_operand: 2 "s_register_operand" "w")))] "TARGET_NEON" "vaddw.\t%q0, %q2, %P1" - [(set_attr "neon_type" "neon_int_3")] + [(set_attr "type" "neon_int_3")] ) ;; VEXT can be used to synthesize coarse whole-vector shifts with 8-bit @@ -1309,7 +1308,7 @@ (define_insn "quad_halves_v4si" "TARGET_NEON" ".32\t%P0, %e1, %f1" [(set_attr "vqh_mnem" "") - (set (attr "neon_type") + (set (attr "type") (if_then_else (eq_attr "vqh_mnem" "vadd") (const_string "neon_int_1") (const_string "neon_int_5")))] ) @@ -1324,7 +1323,7 @@ (define_insn "quad_halves_v4sf" "TARGET_NEON && flag_unsafe_math_optimizations" ".f32\t%P0, %e1, %f1" [(set_attr "vqh_mnem" "") - (set (attr "neon_type") + (set (attr "type") (if_then_else (eq_attr "vqh_mnem" "vadd") (const_string "neon_int_1") (const_string "neon_int_5")))] ) @@ -1341,7 +1340,7 @@ (define_insn "quad_halves_v8hi" "TARGET_NEON" ".16\t%P0, %e1, %f1" [(set_attr "vqh_mnem" "") - (set (attr "neon_type") + (set (attr "type") (if_then_else (eq_attr "vqh_mnem" "vadd") (const_string "neon_int_1") (const_string "neon_int_5")))] ) @@ -1362,7 +1361,7 @@ (define_insn "quad_halves_v16qi" "TARGET_NEON" ".8\t%P0, %e1, %f1" [(set_attr "vqh_mnem" "") - (set (attr "neon_type") + (set (attr "type") (if_then_else (eq_attr "vqh_mnem" "vadd") (const_string "neon_int_1") (const_string "neon_int_5")))] ) @@ -1423,7 +1422,7 @@ (define_insn "reduc_splus_v2di" UNSPEC_VPADD))] "TARGET_NEON && !BYTES_BIG_ENDIAN" "vadd.i64\t%e0, %e1, %f1" - [(set_attr "neon_type" "neon_int_1")] + [(set_attr "type" "neon_int_1")] ) ;; NEON does not distinguish between signed and unsigned addition except on @@ -1547,7 +1546,7 @@ (define_insn "neon_vpadd_internal" "TARGET_NEON" "vpadd.\t%P0, %P1, %P2" ;; Assume this schedules like vadd. - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -1563,7 +1562,7 @@ (define_insn "neon_vpsmin" "TARGET_NEON" "vpmin.\t%P0, %P1, %P2" ;; Assume this schedules like vmin. - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_int_5")))] @@ -1577,7 +1576,7 @@ (define_insn "neon_vpsmax" "TARGET_NEON" "vpmax.\t%P0, %P1, %P2" ;; Assume this schedules like vmax. - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_int_5")))] @@ -1591,7 +1590,7 @@ (define_insn "neon_vpumin" "TARGET_NEON" "vpmin.\t%P0, %P1, %P2" ;; Assume this schedules like umin. - [(set_attr "neon_type" "neon_int_5")] + [(set_attr "type" "neon_int_5")] ) (define_insn "neon_vpumax" @@ -1602,7 +1601,7 @@ (define_insn "neon_vpumax" "TARGET_NEON" "vpmax.\t%P0, %P1, %P2" ;; Assume this schedules like umax. - [(set_attr "neon_type" "neon_int_5")] + [(set_attr "type" "neon_int_5")] ) ;; Saturating arithmetic @@ -1619,7 +1618,7 @@ (define_insn "*ss_add_neon" (match_operand:VD 2 "s_register_operand" "w")))] "TARGET_NEON" "vqadd.\t%P0, %P1, %P2" - [(set_attr "neon_type" "neon_int_4")] + [(set_attr "type" "neon_int_4")] ) (define_insn "*us_add_neon" @@ -1628,7 +1627,7 @@ (define_insn "*us_add_neon" (match_operand:VD 2 "s_register_operand" "w")))] "TARGET_NEON" "vqadd.\t%P0, %P1, %P2" - [(set_attr "neon_type" "neon_int_4")] + [(set_attr "type" "neon_int_4")] ) (define_insn "*ss_sub_neon" @@ -1637,7 +1636,7 @@ (define_insn "*ss_sub_neon" (match_operand:VD 2 "s_register_operand" "w")))] "TARGET_NEON" "vqsub.\t%P0, %P1, %P2" - [(set_attr "neon_type" "neon_int_5")] + [(set_attr "type" "neon_int_5")] ) (define_insn "*us_sub_neon" @@ -1646,7 +1645,7 @@ (define_insn "*us_sub_neon" (match_operand:VD 2 "s_register_operand" "w")))] "TARGET_NEON" "vqsub.\t%P0, %P1, %P2" - [(set_attr "neon_type" "neon_int_5")] + [(set_attr "type" "neon_int_5")] ) ;; Conditional instructions. These are comparisons with conditional moves for @@ -1938,7 +1937,7 @@ (define_insn "neon_vadd_unspec" UNSPEC_VADD))] "TARGET_NEON" "vadd.\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -1958,7 +1957,7 @@ (define_insn "neon_vaddl" UNSPEC_VADDL))] "TARGET_NEON" "vaddl.%T3%#\t%q0, %P1, %P2" - [(set_attr "neon_type" "neon_int_3")] + [(set_attr "type" "neon_int_3")] ) (define_insn "neon_vaddw" @@ -1969,7 +1968,7 @@ (define_insn "neon_vaddw" UNSPEC_VADDW))] "TARGET_NEON" "vaddw.%T3%#\t%q0, %q1, %P2" - [(set_attr "neon_type" "neon_int_2")] + [(set_attr "type" "neon_int_2")] ) ; vhadd and vrhadd. @@ -1982,7 +1981,7 @@ (define_insn "neon_vhadd" UNSPEC_VHADD))] "TARGET_NEON" "v%O3hadd.%T3%#\t%0, %1, %2" - [(set_attr "neon_type" "neon_int_4")] + [(set_attr "type" "neon_int_4")] ) (define_insn "neon_vqadd" @@ -1993,7 +1992,7 @@ (define_insn "neon_vqadd" UNSPEC_VQADD))] "TARGET_NEON" "vqadd.%T3%#\t%0, %1, %2" - [(set_attr "neon_type" "neon_int_4")] + [(set_attr "type" "neon_int_4")] ) (define_insn "neon_vaddhn" @@ -2004,7 +2003,7 @@ (define_insn "neon_vaddhn" UNSPEC_VADDHN))] "TARGET_NEON" "v%O3addhn.\t%P0, %q1, %q2" - [(set_attr "neon_type" "neon_int_4")] + [(set_attr "type" "neon_int_4")] ) ;; We cannot replace this unspec with mul3 because of the odd @@ -2017,7 +2016,7 @@ (define_insn "neon_vmul" UNSPEC_VMUL))] "TARGET_NEON" "vmul.%F3%#\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -2085,7 +2084,7 @@ (define_insn "neon_vmla_unspec" UNSPEC_VMLA))] "TARGET_NEON" "vmla.\t%0, %2, %3" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vmla_ddd") @@ -2109,7 +2108,7 @@ (define_insn "neon_vmlal" UNSPEC_VMLAL))] "TARGET_NEON" "vmlal.%T4%#\t%q0, %P2, %P3" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long") (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))] @@ -2142,7 +2141,7 @@ (define_insn "neon_vmls_unspec" UNSPEC_VMLS))] "TARGET_NEON" "vmls.\t%0, %2, %3" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vmla_ddd") @@ -2167,7 +2166,7 @@ (define_insn "neon_vmlsl" UNSPEC_VMLSL))] "TARGET_NEON" "vmlsl.%T4%#\t%q0, %P2, %P3" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long") (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))] @@ -2181,7 +2180,7 @@ (define_insn "neon_vqdmulh" UNSPEC_VQDMULH))] "TARGET_NEON" "vq%O3dmulh.\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long") @@ -2200,7 +2199,7 @@ (define_insn "neon_vqdmlal" UNSPEC_VQDMLAL))] "TARGET_NEON" "vqdmlal.\t%q0, %P2, %P3" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long") (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))] @@ -2215,7 +2214,7 @@ (define_insn "neon_vqdmlsl" UNSPEC_VQDMLSL))] "TARGET_NEON" "vqdmlsl.\t%q0, %P2, %P3" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long") (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))] @@ -2229,7 +2228,7 @@ (define_insn "neon_vmull" UNSPEC_VMULL))] "TARGET_NEON" "vmull.%T3%#\t%q0, %P1, %P2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long") (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))] @@ -2243,7 +2242,7 @@ (define_insn "neon_vqdmull" UNSPEC_VQDMULL))] "TARGET_NEON" "vqdmull.\t%q0, %P1, %P2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long") (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))] @@ -2273,7 +2272,7 @@ (define_insn "neon_vsub_unspec" UNSPEC_VSUB))] "TARGET_NEON" "vsub.\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -2289,7 +2288,7 @@ (define_insn "neon_vsubl" UNSPEC_VSUBL))] "TARGET_NEON" "vsubl.%T3%#\t%q0, %P1, %P2" - [(set_attr "neon_type" "neon_int_2")] + [(set_attr "type" "neon_int_2")] ) (define_insn "neon_vsubw" @@ -2300,7 +2299,7 @@ (define_insn "neon_vsubw" UNSPEC_VSUBW))] "TARGET_NEON" "vsubw.%T3%#\t%q0, %q1, %P2" - [(set_attr "neon_type" "neon_int_2")] + [(set_attr "type" "neon_int_2")] ) (define_insn "neon_vqsub" @@ -2311,7 +2310,7 @@ (define_insn "neon_vqsub" UNSPEC_VQSUB))] "TARGET_NEON" "vqsub.%T3%#\t%0, %1, %2" - [(set_attr "neon_type" "neon_int_5")] + [(set_attr "type" "neon_int_5")] ) (define_insn "neon_vhsub" @@ -2322,7 +2321,7 @@ (define_insn "neon_vhsub" UNSPEC_VHSUB))] "TARGET_NEON" "vhsub.%T3%#\t%0, %1, %2" - [(set_attr "neon_type" "neon_int_5")] + [(set_attr "type" "neon_int_5")] ) (define_insn "neon_vsubhn" @@ -2333,7 +2332,7 @@ (define_insn "neon_vsubhn" UNSPEC_VSUBHN))] "TARGET_NEON" "v%O3subhn.\t%P0, %q1, %q2" - [(set_attr "neon_type" "neon_int_4")] + [(set_attr "type" "neon_int_4")] ) (define_insn "neon_vceq" @@ -2347,7 +2346,7 @@ (define_insn "neon_vceq" "@ vceq.\t%0, %1, %2 vceq.\t%0, %1, #0" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -2366,7 +2365,7 @@ (define_insn "neon_vcge" "@ vcge.%T3%#\t%0, %1, %2 vcge.%T3%#\t%0, %1, #0" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -2383,7 +2382,7 @@ (define_insn "neon_vcgeu" UNSPEC_VCGEU))] "TARGET_NEON" "vcge.%T3%#\t%0, %1, %2" - [(set_attr "neon_type" "neon_int_5")] + [(set_attr "type" "neon_int_5")] ) (define_insn "neon_vcgt" @@ -2397,7 +2396,7 @@ (define_insn "neon_vcgt" "@ vcgt.%T3%#\t%0, %1, %2 vcgt.%T3%#\t%0, %1, #0" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -2414,7 +2413,7 @@ (define_insn "neon_vcgtu" UNSPEC_VCGTU))] "TARGET_NEON" "vcgt.%T3%#\t%0, %1, %2" - [(set_attr "neon_type" "neon_int_5")] + [(set_attr "type" "neon_int_5")] ) ;; VCLE and VCLT only support comparisons with immediate zero (register @@ -2429,7 +2428,7 @@ (define_insn "neon_vcle" UNSPEC_VCLE))] "TARGET_NEON" "vcle.%T3%#\t%0, %1, #0" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -2446,7 +2445,7 @@ (define_insn "neon_vclt" UNSPEC_VCLT))] "TARGET_NEON" "vclt.%T3%#\t%0, %1, #0" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -2462,7 +2461,7 @@ (define_insn "neon_vcage" UNSPEC_VCAGE))] "TARGET_NEON" "vacge.\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_fp_vadd_qqq_vabs_qq")))] @@ -2476,7 +2475,7 @@ (define_insn "neon_vcagt" UNSPEC_VCAGT))] "TARGET_NEON" "vacgt.\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_fp_vadd_qqq_vabs_qq")))] @@ -2490,7 +2489,7 @@ (define_insn "neon_vtst" UNSPEC_VTST))] "TARGET_NEON" "vtst.\t%0, %1, %2" - [(set_attr "neon_type" "neon_int_4")] + [(set_attr "type" "neon_int_4")] ) (define_insn "neon_vabd" @@ -2501,7 +2500,7 @@ (define_insn "neon_vabd" UNSPEC_VABD))] "TARGET_NEON" "vabd.%T3%#\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -2517,7 +2516,7 @@ (define_insn "neon_vabdl" UNSPEC_VABDL))] "TARGET_NEON" "vabdl.%T3%#\t%q0, %P1, %P2" - [(set_attr "neon_type" "neon_int_5")] + [(set_attr "type" "neon_int_5")] ) (define_insn "neon_vaba" @@ -2529,7 +2528,7 @@ (define_insn "neon_vaba" (match_operand:VDQIW 1 "s_register_operand" "0")))] "TARGET_NEON" "vaba.%T4%#\t%0, %2, %3" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_vaba") (const_string "neon_vaba_qqq")))] ) @@ -2543,7 +2542,7 @@ (define_insn "neon_vabal" (match_operand: 1 "s_register_operand" "0")))] "TARGET_NEON" "vabal.%T4%#\t%q0, %P2, %P3" - [(set_attr "neon_type" "neon_vaba")] + [(set_attr "type" "neon_vaba")] ) (define_insn "neon_vmax" @@ -2554,7 +2553,7 @@ (define_insn "neon_vmax" UNSPEC_VMAX))] "TARGET_NEON" "vmax.%T3%#\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -2570,7 +2569,7 @@ (define_insn "neon_vmin" UNSPEC_VMIN))] "TARGET_NEON" "vmin.%T3%#\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -2598,7 +2597,7 @@ (define_insn "neon_vpaddl" "TARGET_NEON" "vpaddl.%T2%#\t%0, %1" ;; Assume this schedules like vaddl. - [(set_attr "neon_type" "neon_int_3")] + [(set_attr "type" "neon_int_3")] ) (define_insn "neon_vpadal" @@ -2610,7 +2609,7 @@ (define_insn "neon_vpadal" "TARGET_NEON" "vpadal.%T3%#\t%0, %2" ;; Assume this schedules like vpadd. - [(set_attr "neon_type" "neon_int_1")] + [(set_attr "type" "neon_int_1")] ) (define_insn "neon_vpmax" @@ -2622,7 +2621,7 @@ (define_insn "neon_vpmax" "TARGET_NEON" "vpmax.%T3%#\t%0, %1, %2" ;; Assume this schedules like vmax. - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_int_5")))] @@ -2637,7 +2636,7 @@ (define_insn "neon_vpmin" "TARGET_NEON" "vpmin.%T3%#\t%0, %1, %2" ;; Assume this schedules like vmin. - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_int_5")))] @@ -2651,7 +2650,7 @@ (define_insn "neon_vrecps" UNSPEC_VRECPS))] "TARGET_NEON" "vrecps.\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vrecps_vrsqrts_ddd") (const_string "neon_fp_vrecps_vrsqrts_qqq")))] @@ -2665,7 +2664,7 @@ (define_insn "neon_vrsqrts" UNSPEC_VRSQRTS))] "TARGET_NEON" "vrsqrts.\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vrecps_vrsqrts_ddd") (const_string "neon_fp_vrecps_vrsqrts_qqq")))] @@ -2688,7 +2687,7 @@ (define_insn "neon_vqabs" UNSPEC_VQABS))] "TARGET_NEON" "vqabs.\t%0, %1" - [(set_attr "neon_type" "neon_vqneg_vqabs")] + [(set_attr "type" "neon_vqneg_vqabs")] ) (define_expand "neon_vneg" @@ -2708,7 +2707,7 @@ (define_insn "neon_vqneg" UNSPEC_VQNEG))] "TARGET_NEON" "vqneg.\t%0, %1" - [(set_attr "neon_type" "neon_vqneg_vqabs")] + [(set_attr "type" "neon_vqneg_vqabs")] ) (define_insn "neon_vcls" @@ -2718,7 +2717,7 @@ (define_insn "neon_vcls" UNSPEC_VCLS))] "TARGET_NEON" "vcls.\t%0, %1" - [(set_attr "neon_type" "neon_int_1")] + [(set_attr "type" "neon_int_1")] ) (define_insn "clz2" @@ -2726,7 +2725,7 @@ (define_insn "clz2" (clz:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")))] "TARGET_NEON" "vclz.\t%0, %1" - [(set_attr "neon_type" "neon_int_1")] + [(set_attr "type" "neon_int_1")] ) (define_expand "neon_vclz" @@ -2744,7 +2743,7 @@ (define_insn "popcount2" (popcount:VE (match_operand:VE 1 "s_register_operand" "w")))] "TARGET_NEON" "vcnt.\t%0, %1" - [(set_attr "neon_type" "neon_int_1")] + [(set_attr "type" "neon_int_1")] ) (define_expand "neon_vcnt" @@ -2764,7 +2763,7 @@ (define_insn "neon_vrecpe" UNSPEC_VRECPE))] "TARGET_NEON" "vrecpe.\t%0, %1" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_fp_vadd_qqq_vabs_qq")))] @@ -2777,7 +2776,7 @@ (define_insn "neon_vrsqrte" UNSPEC_VRSQRTE))] "TARGET_NEON" "vrsqrte.\t%0, %1" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_fp_vadd_qqq_vabs_qq")))] @@ -2809,7 +2808,7 @@ (define_insn "neon_vget_lane_sext_ } return "vmov.s\t%0, %P1[%c2]"; } - [(set_attr "neon_type" "neon_bp_simple")] + [(set_attr "type" "neon_bp_simple")] ) (define_insn "neon_vget_lane_zext_internal" @@ -2828,7 +2827,7 @@ (define_insn "neon_vget_lane_zext_ } return "vmov.u\t%0, %P1[%c2]"; } - [(set_attr "neon_type" "neon_bp_simple")] + [(set_attr "type" "neon_bp_simple")] ) (define_insn "neon_vget_lane_sext_internal" @@ -2855,7 +2854,7 @@ (define_insn "neon_vget_lane_sext_ return ""; } - [(set_attr "neon_type" "neon_bp_simple")] + [(set_attr "type" "neon_bp_simple")] ) (define_insn "neon_vget_lane_zext_internal" @@ -2882,7 +2881,7 @@ (define_insn "neon_vget_lane_zext_ return ""; } - [(set_attr "neon_type" "neon_bp_simple")] + [(set_attr "type" "neon_bp_simple")] ) (define_expand "neon_vget_lane" @@ -3015,7 +3014,7 @@ (define_insn "neon_vdup_n" "TARGET_NEON" "vdup.\t%0, %1" ;; Assume this schedules like vmov. - [(set_attr "neon_type" "neon_bp_simple")] + [(set_attr "type" "neon_bp_simple")] ) (define_insn "neon_vdup_n" @@ -3026,7 +3025,7 @@ (define_insn "neon_vdup_n" vdup.\t%0, %1 vdup.\t%0, %y1" ;; Assume this schedules like vmov. - [(set_attr "neon_type" "neon_bp_simple")] + [(set_attr "type" "neon_bp_simple")] ) (define_expand "neon_vdup_ndi" @@ -3047,7 +3046,7 @@ (define_insn "neon_vdup_nv2di" vmov\t%e0, %Q1, %R1\;vmov\t%f0, %Q1, %R1 vmov\t%e0, %P1\;vmov\t%f0, %P1" [(set_attr "length" "8") - (set_attr "neon_type" "neon_bp_simple")] + (set_attr "type" "neon_bp_simple")] ) (define_insn "neon_vdup_lane_internal" @@ -3070,7 +3069,7 @@ (define_insn "neon_vdup_lane_inter return "vdup.\t%q0, %P1[%c2]"; } ;; Assume this schedules like vmov. - [(set_attr "neon_type" "neon_bp_simple")] + [(set_attr "type" "neon_bp_simple")] ) (define_expand "neon_vdup_lane" @@ -3125,7 +3124,7 @@ (define_insn "*neon_vswp" (set (match_dup 1) (match_dup 0))] "TARGET_NEON && reload_completed" "vswp\t%0, %1" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_bp_simple") (const_string "neon_bp_2cycle")))] @@ -3179,7 +3178,7 @@ (define_insn "float2" (float: (match_operand:VCVTI 1 "s_register_operand" "w")))] "TARGET_NEON && !flag_rounding_math" "vcvt.f32.s32\t%0, %1" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_fp_vadd_qqq_vabs_qq")))] @@ -3190,7 +3189,7 @@ (define_insn "floatuns2" (unsigned_float: (match_operand:VCVTI 1 "s_register_operand" "w")))] "TARGET_NEON && !flag_rounding_math" "vcvt.f32.u32\t%0, %1" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_fp_vadd_qqq_vabs_qq")))] @@ -3201,7 +3200,7 @@ (define_insn "fix_trunc2" (fix: (match_operand:VCVTF 1 "s_register_operand" "w")))] "TARGET_NEON" "vcvt.s32.f32\t%0, %1" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_fp_vadd_qqq_vabs_qq")))] @@ -3212,7 +3211,7 @@ (define_insn "fixuns_trunc (match_operand:VCVTF 1 "s_register_operand" "w")))] "TARGET_NEON" "vcvt.u32.f32\t%0, %1" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_fp_vadd_qqq_vabs_qq")))] @@ -3225,7 +3224,7 @@ (define_insn "neon_vcvt" UNSPEC_VCVT))] "TARGET_NEON" "vcvt.%T2%#32.f32\t%0, %1" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_fp_vadd_qqq_vabs_qq")))] @@ -3238,7 +3237,7 @@ (define_insn "neon_vcvt" UNSPEC_VCVT))] "TARGET_NEON" "vcvt.f32.%T2%#32\t%0, %1" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_fp_vadd_qqq_vabs_qq")))] @@ -3250,7 +3249,7 @@ (define_insn "neon_vcvtv4sfv4hf" UNSPEC_VCVT))] "TARGET_NEON && TARGET_FP16" "vcvt.f32.f16\t%q0, %P1" - [(set_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd")] + [(set_attr "type" "neon_fp_vadd_ddd_vabs_dd")] ) (define_insn "neon_vcvtv4hfv4sf" @@ -3259,7 +3258,7 @@ (define_insn "neon_vcvtv4hfv4sf" UNSPEC_VCVT))] "TARGET_NEON && TARGET_FP16" "vcvt.f16.f32\t%P0, %q1" - [(set_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd")] + [(set_attr "type" "neon_fp_vadd_ddd_vabs_dd")] ) (define_insn "neon_vcvt_n" @@ -3273,7 +3272,7 @@ (define_insn "neon_vcvt_n" neon_const_bounds (operands[2], 1, 33); return "vcvt.%T3%#32.f32\t%0, %1, %2"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_fp_vadd_qqq_vabs_qq")))] @@ -3290,7 +3289,7 @@ (define_insn "neon_vcvt_n" neon_const_bounds (operands[2], 1, 33); return "vcvt.f32.%T3%#32\t%0, %1, %2"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vadd_ddd_vabs_dd") (const_string "neon_fp_vadd_qqq_vabs_qq")))] @@ -3303,7 +3302,7 @@ (define_insn "neon_vmovn" UNSPEC_VMOVN))] "TARGET_NEON" "vmovn.\t%P0, %q1" - [(set_attr "neon_type" "neon_bp_simple")] + [(set_attr "type" "neon_bp_simple")] ) (define_insn "neon_vqmovn" @@ -3313,7 +3312,7 @@ (define_insn "neon_vqmovn" UNSPEC_VQMOVN))] "TARGET_NEON" "vqmovn.%T2%#\t%P0, %q1" - [(set_attr "neon_type" "neon_shift_2")] + [(set_attr "type" "neon_shift_2")] ) (define_insn "neon_vqmovun" @@ -3323,7 +3322,7 @@ (define_insn "neon_vqmovun" UNSPEC_VQMOVUN))] "TARGET_NEON" "vqmovun.\t%P0, %q1" - [(set_attr "neon_type" "neon_shift_2")] + [(set_attr "type" "neon_shift_2")] ) (define_insn "neon_vmovl" @@ -3333,7 +3332,7 @@ (define_insn "neon_vmovl" UNSPEC_VMOVL))] "TARGET_NEON" "vmovl.%T2%#\t%q0, %P1" - [(set_attr "neon_type" "neon_shift_1")] + [(set_attr "type" "neon_shift_1")] ) (define_insn "neon_vmul_lane" @@ -3349,7 +3348,7 @@ (define_insn "neon_vmul_lane" neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); return "vmul.\t%P0, %P1, %P2[%c3]"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vmul_ddd") (if_then_else (match_test "") @@ -3370,7 +3369,7 @@ (define_insn "neon_vmul_lane" neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); return "vmul.\t%q0, %q1, %P2[%c3]"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vmul_qqd") (if_then_else (match_test "") @@ -3391,7 +3390,7 @@ (define_insn "neon_vmull_lane" neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); return "vmull.%T4%#\t%q0, %P1, %P2[%c3]"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_mul_ddd_16_scalar_32_16_long_scalar") (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))] @@ -3410,7 +3409,7 @@ (define_insn "neon_vqdmull_lane" neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); return "vqdmull.\t%q0, %P1, %P2[%c3]"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_mul_ddd_16_scalar_32_16_long_scalar") (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))] @@ -3429,7 +3428,7 @@ (define_insn "neon_vqdmulh_lane" neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); return "vq%O4dmulh.%T4%#\t%q0, %q1, %P2[%c3]"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar") (const_string "neon_mul_qqd_32_scalar")))] @@ -3448,7 +3447,7 @@ (define_insn "neon_vqdmulh_lane" neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); return "vq%O4dmulh.%T4%#\t%P0, %P1, %P2[%c3]"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_mul_ddd_16_scalar_32_16_long_scalar") (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))] @@ -3468,7 +3467,7 @@ (define_insn "neon_vmla_lane" neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); return "vmla.\t%P0, %P2, %P3[%c4]"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vmla_ddd_scalar") (if_then_else (match_test "") @@ -3490,7 +3489,7 @@ (define_insn "neon_vmla_lane" neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); return "vmla.\t%q0, %q2, %P3[%c4]"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vmla_qqq_scalar") (if_then_else (match_test "") @@ -3512,7 +3511,7 @@ (define_insn "neon_vmlal_lane" neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); return "vmlal.%T5%#\t%q0, %P2, %P3[%c4]"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar") (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))] @@ -3532,7 +3531,7 @@ (define_insn "neon_vqdmlal_lane" neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); return "vqdmlal.\t%q0, %P2, %P3[%c4]"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar") (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))] @@ -3552,7 +3551,7 @@ (define_insn "neon_vmls_lane" neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); return "vmls.\t%P0, %P2, %P3[%c4]"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vmla_ddd_scalar") (if_then_else (match_test "") @@ -3574,7 +3573,7 @@ (define_insn "neon_vmls_lane" neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); return "vmls.\t%q0, %q2, %P3[%c4]"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_fp_vmla_qqq_scalar") (if_then_else (match_test "") @@ -3596,7 +3595,7 @@ (define_insn "neon_vmlsl_lane" neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); return "vmlsl.%T5%#\t%q0, %P2, %P3[%c4]"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar") (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))] @@ -3616,7 +3615,7 @@ (define_insn "neon_vqdmlsl_lane" neon_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); return "vqdmlsl.\t%q0, %P2, %P3[%c4]"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar") (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))] @@ -3844,7 +3843,7 @@ (define_insn "neon_vext" neon_const_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); return "vext.\t%0, %1, %2, %3"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_bp_simple") (const_string "neon_bp_2cycle")))] @@ -3857,7 +3856,7 @@ (define_insn "neon_vrev64" UNSPEC_VREV64))] "TARGET_NEON" "vrev64.\t%0, %1" - [(set_attr "neon_type" "neon_bp_simple")] + [(set_attr "type" "neon_bp_simple")] ) (define_insn "neon_vrev32" @@ -3867,7 +3866,7 @@ (define_insn "neon_vrev32" UNSPEC_VREV32))] "TARGET_NEON" "vrev32.\t%0, %1" - [(set_attr "neon_type" "neon_bp_simple")] + [(set_attr "type" "neon_bp_simple")] ) (define_insn "neon_vrev16" @@ -3877,7 +3876,7 @@ (define_insn "neon_vrev16" UNSPEC_VREV16))] "TARGET_NEON" "vrev16.\t%0, %1" - [(set_attr "neon_type" "neon_bp_simple")] + [(set_attr "type" "neon_bp_simple")] ) ; vbsl_* intrinsics may compile to any of vbsl/vbif/vbit depending on register @@ -3899,7 +3898,7 @@ (define_insn "neon_vbsl_internal" vbsl\t%0, %2, %3 vbit\t%0, %2, %1 vbif\t%0, %3, %1" - [(set_attr "neon_type" "neon_int_1")] + [(set_attr "type" "neon_int_1")] ) (define_expand "neon_vbsl" @@ -3922,7 +3921,7 @@ (define_insn "neon_vshl" UNSPEC_VSHL))] "TARGET_NEON" "v%O3shl.%T3%#\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_vshl_ddd") (const_string "neon_shift_3")))] @@ -3936,7 +3935,7 @@ (define_insn "neon_vqshl" UNSPEC_VQSHL))] "TARGET_NEON" "vq%O3shl.%T3%#\t%0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_shift_2") (const_string "neon_vqshl_vrshl_vqrshl_qqq")))] @@ -3953,7 +3952,7 @@ (define_insn "neon_vshr_n" neon_const_bounds (operands[2], 1, neon_element_bits (mode) + 1); return "v%O3shr.%T3%#\t%0, %1, %2"; } - [(set_attr "neon_type" "neon_shift_1")] + [(set_attr "type" "neon_shift_1")] ) (define_insn "neon_vshrn_n" @@ -3967,7 +3966,7 @@ (define_insn "neon_vshrn_n" neon_const_bounds (operands[2], 1, neon_element_bits (mode) / 2 + 1); return "v%O3shrn.\t%P0, %q1, %2"; } - [(set_attr "neon_type" "neon_shift_1")] + [(set_attr "type" "neon_shift_1")] ) (define_insn "neon_vqshrn_n" @@ -3981,7 +3980,7 @@ (define_insn "neon_vqshrn_n" neon_const_bounds (operands[2], 1, neon_element_bits (mode) / 2 + 1); return "vq%O3shrn.%T3%#\t%P0, %q1, %2"; } - [(set_attr "neon_type" "neon_shift_2")] + [(set_attr "type" "neon_shift_2")] ) (define_insn "neon_vqshrun_n" @@ -3995,7 +3994,7 @@ (define_insn "neon_vqshrun_n" neon_const_bounds (operands[2], 1, neon_element_bits (mode) / 2 + 1); return "vq%O3shrun.%T3%#\t%P0, %q1, %2"; } - [(set_attr "neon_type" "neon_shift_2")] + [(set_attr "type" "neon_shift_2")] ) (define_insn "neon_vshl_n" @@ -4009,7 +4008,7 @@ (define_insn "neon_vshl_n" neon_const_bounds (operands[2], 0, neon_element_bits (mode)); return "vshl.\t%0, %1, %2"; } - [(set_attr "neon_type" "neon_shift_1")] + [(set_attr "type" "neon_shift_1")] ) (define_insn "neon_vqshl_n" @@ -4023,7 +4022,7 @@ (define_insn "neon_vqshl_n" neon_const_bounds (operands[2], 0, neon_element_bits (mode)); return "vqshl.%T3%#\t%0, %1, %2"; } - [(set_attr "neon_type" "neon_shift_2")] + [(set_attr "type" "neon_shift_2")] ) (define_insn "neon_vqshlu_n" @@ -4037,7 +4036,7 @@ (define_insn "neon_vqshlu_n" neon_const_bounds (operands[2], 0, neon_element_bits (mode)); return "vqshlu.%T3%#\t%0, %1, %2"; } - [(set_attr "neon_type" "neon_shift_2")] + [(set_attr "type" "neon_shift_2")] ) (define_insn "neon_vshll_n" @@ -4052,7 +4051,7 @@ (define_insn "neon_vshll_n" neon_const_bounds (operands[2], 0, neon_element_bits (mode) + 1); return "vshll.%T3%#\t%q0, %P1, %2"; } - [(set_attr "neon_type" "neon_shift_1")] + [(set_attr "type" "neon_shift_1")] ) (define_insn "neon_vsra_n" @@ -4067,7 +4066,7 @@ (define_insn "neon_vsra_n" neon_const_bounds (operands[3], 1, neon_element_bits (mode) + 1); return "v%O4sra.%T4%#\t%0, %2, %3"; } - [(set_attr "neon_type" "neon_vsra_vrsra")] + [(set_attr "type" "neon_vsra_vrsra")] ) (define_insn "neon_vsri_n" @@ -4081,7 +4080,7 @@ (define_insn "neon_vsri_n" neon_const_bounds (operands[3], 1, neon_element_bits (mode) + 1); return "vsri.\t%0, %2, %3"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_shift_1") (const_string "neon_shift_3")))] @@ -4098,7 +4097,7 @@ (define_insn "neon_vsli_n" neon_const_bounds (operands[3], 0, neon_element_bits (mode)); return "vsli.\t%0, %2, %3"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_shift_1") (const_string "neon_shift_3")))] @@ -4111,7 +4110,7 @@ (define_insn "neon_vtbl1v8qi" UNSPEC_VTBL))] "TARGET_NEON" "vtbl.8\t%P0, {%P1}, %P2" - [(set_attr "neon_type" "neon_bp_2cycle")] + [(set_attr "type" "neon_bp_2cycle")] ) (define_insn "neon_vtbl2v8qi" @@ -4132,7 +4131,7 @@ (define_insn "neon_vtbl2v8qi" return ""; } - [(set_attr "neon_type" "neon_bp_2cycle")] + [(set_attr "type" "neon_bp_2cycle")] ) (define_insn "neon_vtbl3v8qi" @@ -4154,7 +4153,7 @@ (define_insn "neon_vtbl3v8qi" return ""; } - [(set_attr "neon_type" "neon_bp_3cycle")] + [(set_attr "type" "neon_bp_3cycle")] ) (define_insn "neon_vtbl4v8qi" @@ -4177,7 +4176,7 @@ (define_insn "neon_vtbl4v8qi" return ""; } - [(set_attr "neon_type" "neon_bp_3cycle")] + [(set_attr "type" "neon_bp_3cycle")] ) ;; These three are used by the vec_perm infrastructure for V16QImode. @@ -4265,7 +4264,7 @@ (define_insn "neon_vtbx1v8qi" UNSPEC_VTBX))] "TARGET_NEON" "vtbx.8\t%P0, {%P2}, %P3" - [(set_attr "neon_type" "neon_bp_2cycle")] + [(set_attr "type" "neon_bp_2cycle")] ) (define_insn "neon_vtbx2v8qi" @@ -4287,7 +4286,7 @@ (define_insn "neon_vtbx2v8qi" return ""; } - [(set_attr "neon_type" "neon_bp_2cycle")] + [(set_attr "type" "neon_bp_2cycle")] ) (define_insn "neon_vtbx3v8qi" @@ -4310,7 +4309,7 @@ (define_insn "neon_vtbx3v8qi" return ""; } - [(set_attr "neon_type" "neon_bp_3cycle")] + [(set_attr "type" "neon_bp_3cycle")] ) (define_insn "neon_vtbx4v8qi" @@ -4334,7 +4333,7 @@ (define_insn "neon_vtbx4v8qi" return ""; } - [(set_attr "neon_type" "neon_bp_3cycle")] + [(set_attr "type" "neon_bp_3cycle")] ) (define_expand "neon_vtrn_internal" @@ -4360,7 +4359,7 @@ (define_insn "*neon_vtrn_insn" UNSPEC_VTRN2))] "TARGET_NEON" "vtrn.\t%0, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_bp_simple") (const_string "neon_bp_3cycle")))] @@ -4400,7 +4399,7 @@ (define_insn "*neon_vzip_insn" UNSPEC_VZIP2))] "TARGET_NEON" "vzip.\t%0, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_bp_simple") (const_string "neon_bp_3cycle")))] @@ -4440,7 +4439,7 @@ (define_insn "*neon_vuzp_insn" UNSPEC_VUZP2))] "TARGET_NEON" "vuzp.\t%0, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (match_test "") (const_string "neon_bp_simple") (const_string "neon_bp_3cycle")))] @@ -4559,7 +4558,7 @@ (define_insn "neon_vld1" UNSPEC_VLD1))] "TARGET_NEON" "vld1.\t%h0, %A1" - [(set_attr "neon_type" "neon_vld1_1_2_regs")] + [(set_attr "type" "neon_vld1_1_2_regs")] ) (define_insn "neon_vld1_lane" @@ -4579,7 +4578,7 @@ (define_insn "neon_vld1_lane" else return "vld1.\t{%P0[%c3]}, %A1"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (eq (const_string "") (const_int 2)) (const_string "neon_vld1_1_2_regs") (const_string "neon_vld1_vld2_lane")))] @@ -4610,7 +4609,7 @@ (define_insn "neon_vld1_lane" else return "vld1.\t{%P0[%c3]}, %A1"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (eq (const_string "") (const_int 2)) (const_string "neon_vld1_1_2_regs") (const_string "neon_vld1_vld2_lane")))] @@ -4621,7 +4620,7 @@ (define_insn "neon_vld1_dup" (vec_duplicate:VD (match_operand: 1 "neon_struct_operand" "Um")))] "TARGET_NEON" "vld1.\t{%P0[]}, %A1" - [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")] + [(set_attr "type" "neon_vld2_2_regs_vld1_vld2_all_lanes")] ) ;; Special case for DImode. Treat it exactly like a simple load. @@ -4640,7 +4639,7 @@ (define_insn "neon_vld1_dup" { return "vld1.\t{%e0[], %f0[]}, %A1"; } - [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")] + [(set_attr "type" "neon_vld2_2_regs_vld1_vld2_all_lanes")] ) (define_insn_and_split "neon_vld1_dupv2di" @@ -4657,7 +4656,7 @@ (define_insn_and_split "neon_vld1_dupv2d DONE; } [(set_attr "length" "8") - (set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")] + (set_attr "type" "neon_vld2_2_regs_vld1_vld2_all_lanes")] ) (define_expand "vec_store_lanes" @@ -4672,7 +4671,7 @@ (define_insn "neon_vst1" UNSPEC_VST1))] "TARGET_NEON" "vst1.\t%h1, %A0" - [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) + [(set_attr "type" "neon_vst1_1_2_regs_vst2_2_regs")]) (define_insn "neon_vst1_lane" [(set (match_operand: 0 "neon_struct_operand" "=Um") @@ -4691,7 +4690,7 @@ (define_insn "neon_vst1_lane" else return "vst1.\t{%P1[%c2]}, %A0"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (eq (const_string "") (const_int 1)) (const_string "neon_vst1_1_2_regs_vst2_2_regs") (const_string "neon_vst1_vst2_lane")))]) @@ -4721,7 +4720,7 @@ (define_insn "neon_vst1_lane" else return "vst1.\t{%P1[%c2]}, %A0"; } - [(set_attr "neon_type" "neon_vst1_vst2_lane")] + [(set_attr "type" "neon_vst1_vst2_lane")] ) (define_expand "vec_load_lanesti" @@ -4743,7 +4742,7 @@ (define_insn "neon_vld2" else return "vld2.\t%h0, %A1"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (eq (const_string "") (const_string "64")) (const_string "neon_vld1_1_2_regs") (const_string "neon_vld2_2_regs_vld1_vld2_all_lanes")))] @@ -4763,7 +4762,7 @@ (define_insn "neon_vld2" UNSPEC_VLD2))] "TARGET_NEON" "vld2.\t%h0, %A1" - [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")]) + [(set_attr "type" "neon_vld2_2_regs_vld1_vld2_all_lanes")]) (define_insn "neon_vld2_lane" [(set (match_operand:TI 0 "s_register_operand" "=w") @@ -4787,7 +4786,7 @@ (define_insn "neon_vld2_lane" output_asm_insn ("vld2.\t{%P0[%c3], %P1[%c3]}, %A2", ops); return ""; } - [(set_attr "neon_type" "neon_vld1_vld2_lane")] + [(set_attr "type" "neon_vld1_vld2_lane")] ) (define_insn "neon_vld2_lane" @@ -4817,7 +4816,7 @@ (define_insn "neon_vld2_lane" output_asm_insn ("vld2.\t{%P0[%c3], %P1[%c3]}, %A2", ops); return ""; } - [(set_attr "neon_type" "neon_vld1_vld2_lane")] + [(set_attr "type" "neon_vld1_vld2_lane")] ) (define_insn "neon_vld2_dup" @@ -4832,7 +4831,7 @@ (define_insn "neon_vld2_dup" else return "vld1.\t%h0, %A1"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (gt (const_string "") (const_string "1")) (const_string "neon_vld2_2_regs_vld1_vld2_all_lanes") (const_string "neon_vld1_1_2_regs")))] @@ -4857,7 +4856,7 @@ (define_insn "neon_vst2" else return "vst2.\t%h1, %A0"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (eq (const_string "") (const_string "64")) (const_string "neon_vst1_1_2_regs_vst2_2_regs") (const_string "neon_vst1_1_2_regs_vst2_2_regs")))] @@ -4877,7 +4876,7 @@ (define_insn "neon_vst2" UNSPEC_VST2))] "TARGET_NEON" "vst2.\t%h1, %A0" - [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")] + [(set_attr "type" "neon_vst1_1_2_regs_vst2_2_regs")] ) (define_insn "neon_vst2_lane" @@ -4902,7 +4901,7 @@ (define_insn "neon_vst2_lane" output_asm_insn ("vst2.\t{%P1[%c3], %P2[%c3]}, %A0", ops); return ""; } - [(set_attr "neon_type" "neon_vst1_vst2_lane")] + [(set_attr "type" "neon_vst1_vst2_lane")] ) (define_insn "neon_vst2_lane" @@ -4932,7 +4931,7 @@ (define_insn "neon_vst2_lane" output_asm_insn ("vst2.\t{%P1[%c3], %P2[%c3]}, %A0", ops); return ""; } - [(set_attr "neon_type" "neon_vst1_vst2_lane")] + [(set_attr "type" "neon_vst1_vst2_lane")] ) (define_expand "vec_load_lanesei" @@ -4954,7 +4953,7 @@ (define_insn "neon_vld3" else return "vld3.\t%h0, %A1"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (eq (const_string "") (const_string "64")) (const_string "neon_vld1_1_2_regs") (const_string "neon_vld3_vld4")))] @@ -5001,7 +5000,7 @@ (define_insn "neon_vld3qa" output_asm_insn ("vld3.\t{%P0, %P1, %P2}, %A3", ops); return ""; } - [(set_attr "neon_type" "neon_vld3_vld4")] + [(set_attr "type" "neon_vld3_vld4")] ) (define_insn "neon_vld3qb" @@ -5021,7 +5020,7 @@ (define_insn "neon_vld3qb" output_asm_insn ("vld3.\t{%P0, %P1, %P2}, %A3", ops); return ""; } - [(set_attr "neon_type" "neon_vld3_vld4")] + [(set_attr "type" "neon_vld3_vld4")] ) (define_insn "neon_vld3_lane" @@ -5048,7 +5047,7 @@ (define_insn "neon_vld3_lane" ops); return ""; } - [(set_attr "neon_type" "neon_vld3_vld4_lane")] + [(set_attr "type" "neon_vld3_vld4_lane")] ) (define_insn "neon_vld3_lane" @@ -5080,7 +5079,7 @@ (define_insn "neon_vld3_lane" ops); return ""; } - [(set_attr "neon_type" "neon_vld3_vld4_lane")] + [(set_attr "type" "neon_vld3_vld4_lane")] ) (define_insn "neon_vld3_dup" @@ -5104,7 +5103,7 @@ (define_insn "neon_vld3_dup" else return "vld1.\t%h0, %A1"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (gt (const_string "") (const_string "1")) (const_string "neon_vld3_vld4_all_lanes") (const_string "neon_vld1_1_2_regs")))]) @@ -5128,7 +5127,7 @@ (define_insn "neon_vst3" else return "vst3.\t%h1, %A0"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (eq (const_string "") (const_string "64")) (const_string "neon_vst1_1_2_regs_vst2_2_regs") (const_string "neon_vst2_4_regs_vst3_vst4")))]) @@ -5174,7 +5173,7 @@ (define_insn "neon_vst3qa" output_asm_insn ("vst3.\t{%P1, %P2, %P3}, %A0", ops); return ""; } - [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] + [(set_attr "type" "neon_vst2_4_regs_vst3_vst4")] ) (define_insn "neon_vst3qb" @@ -5193,7 +5192,7 @@ (define_insn "neon_vst3qb" output_asm_insn ("vst3.\t{%P1, %P2, %P3}, %A0", ops); return ""; } - [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] + [(set_attr "type" "neon_vst2_4_regs_vst3_vst4")] ) (define_insn "neon_vst3_lane" @@ -5220,7 +5219,7 @@ (define_insn "neon_vst3_lane" ops); return ""; } - [(set_attr "neon_type" "neon_vst3_vst4_lane")] + [(set_attr "type" "neon_vst3_vst4_lane")] ) (define_insn "neon_vst3_lane" @@ -5252,7 +5251,7 @@ (define_insn "neon_vst3_lane" ops); return ""; } -[(set_attr "neon_type" "neon_vst3_vst4_lane")]) +[(set_attr "type" "neon_vst3_vst4_lane")]) (define_expand "vec_load_lanesoi" [(set (match_operand:OI 0 "s_register_operand") @@ -5273,7 +5272,7 @@ (define_insn "neon_vld4" else return "vld4.\t%h0, %A1"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (eq (const_string "") (const_string "64")) (const_string "neon_vld1_1_2_regs") (const_string "neon_vld3_vld4")))] @@ -5321,7 +5320,7 @@ (define_insn "neon_vld4qa" output_asm_insn ("vld4.\t{%P0, %P1, %P2, %P3}, %A4", ops); return ""; } - [(set_attr "neon_type" "neon_vld3_vld4")] + [(set_attr "type" "neon_vld3_vld4")] ) (define_insn "neon_vld4qb" @@ -5342,7 +5341,7 @@ (define_insn "neon_vld4qb" output_asm_insn ("vld4.\t{%P0, %P1, %P2, %P3}, %A4", ops); return ""; } - [(set_attr "neon_type" "neon_vld3_vld4")] + [(set_attr "type" "neon_vld3_vld4")] ) (define_insn "neon_vld4_lane" @@ -5370,7 +5369,7 @@ (define_insn "neon_vld4_lane" ops); return ""; } - [(set_attr "neon_type" "neon_vld3_vld4_lane")] + [(set_attr "type" "neon_vld3_vld4_lane")] ) (define_insn "neon_vld4_lane" @@ -5403,7 +5402,7 @@ (define_insn "neon_vld4_lane" ops); return ""; } - [(set_attr "neon_type" "neon_vld3_vld4_lane")] + [(set_attr "type" "neon_vld3_vld4_lane")] ) (define_insn "neon_vld4_dup" @@ -5429,7 +5428,7 @@ (define_insn "neon_vld4_dup" else return "vld1.\t%h0, %A1"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (gt (const_string "") (const_string "1")) (const_string "neon_vld3_vld4_all_lanes") (const_string "neon_vld1_1_2_regs")))] @@ -5454,7 +5453,7 @@ (define_insn "neon_vst4" else return "vst4.\t%h1, %A0"; } - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (eq (const_string "") (const_string "64")) (const_string "neon_vst1_1_2_regs_vst2_2_regs") (const_string "neon_vst2_4_regs_vst3_vst4")))] @@ -5502,7 +5501,7 @@ (define_insn "neon_vst4qa" output_asm_insn ("vst4.\t{%P1, %P2, %P3, %P4}, %A0", ops); return ""; } - [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] + [(set_attr "type" "neon_vst2_4_regs_vst3_vst4")] ) (define_insn "neon_vst4qb" @@ -5522,7 +5521,7 @@ (define_insn "neon_vst4qb" output_asm_insn ("vst4.\t{%P1, %P2, %P3, %P4}, %A0", ops); return ""; } - [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] + [(set_attr "type" "neon_vst2_4_regs_vst3_vst4")] ) (define_insn "neon_vst4_lane" @@ -5550,7 +5549,7 @@ (define_insn "neon_vst4_lane" ops); return ""; } - [(set_attr "neon_type" "neon_vst3_vst4_lane")] + [(set_attr "type" "neon_vst3_vst4_lane")] ) (define_insn "neon_vst4_lane" @@ -5583,7 +5582,7 @@ (define_insn "neon_vst4_lane" ops); return ""; } - [(set_attr "neon_type" "neon_vst3_vst4_lane")] + [(set_attr "type" "neon_vst3_vst4_lane")] ) (define_expand "neon_vand" @@ -5648,7 +5647,7 @@ (define_insn "neon_vec_unpack_lo_ %q0, %e1" - [(set_attr "neon_type" "neon_shift_1")] + [(set_attr "type" "neon_shift_1")] ) (define_insn "neon_vec_unpack_hi_" @@ -5658,7 +5657,7 @@ (define_insn "neon_vec_unpack_hi_ %q0, %f1" - [(set_attr "neon_type" "neon_shift_1")] + [(set_attr "type" "neon_shift_1")] ) (define_expand "vec_unpack_hi_" @@ -5708,7 +5707,7 @@ (define_insn "neon_vec_mult_lo_ %q0, %e1, %e3" - [(set_attr "neon_type" "neon_shift_1")] + [(set_attr "type" "neon_shift_1")] ) (define_expand "vec_widen_mult_lo_" @@ -5742,7 +5741,7 @@ (define_insn "neon_vec_mult_hi_ %q0, %f1, %f3" - [(set_attr "neon_type" "neon_shift_1")] + [(set_attr "type" "neon_shift_1")] ) (define_expand "vec_widen_mult_hi_" @@ -5775,7 +5774,7 @@ (define_insn "neon_vec_shiftl_ { return "vshll. %q0, %P1, %2"; } - [(set_attr "neon_type" "neon_shift_1")] + [(set_attr "type" "neon_shift_1")] ) (define_expand "vec_widen_shiftl_lo_" @@ -5811,7 +5810,7 @@ (define_insn "neon_unpack_" (SE: (match_operand:VDI 1 "register_operand" "w")))] "TARGET_NEON" "vmovl. %q0, %P1" - [(set_attr "neon_type" "neon_shift_1")] + [(set_attr "type" "neon_shift_1")] ) (define_expand "vec_unpack_lo_" @@ -5848,7 +5847,7 @@ (define_insn "neon_vec_mult_" (match_operand:VDI 2 "register_operand" "w"))))] "TARGET_NEON" "vmull. %q0, %P1, %P2" - [(set_attr "neon_type" "neon_shift_1")] + [(set_attr "type" "neon_shift_1")] ) (define_expand "vec_widen_mult_hi_" @@ -5922,7 +5921,7 @@ (define_insn "vec_pack_trunc_" (match_operand:VN 2 "register_operand" "w"))))] "TARGET_NEON && !BYTES_BIG_ENDIAN" "vmovn.i\t%e0, %q1\;vmovn.i\t%f0, %q2" - [(set_attr "neon_type" "neon_shift_1") + [(set_attr "type" "neon_shift_1") (set_attr "length" "8")] ) @@ -5932,7 +5931,7 @@ (define_insn "neon_vec_pack_trunc_ (truncate: (match_operand:VN 1 "register_operand" "w")))] "TARGET_NEON && !BYTES_BIG_ENDIAN" "vmovn.i\t%P0, %q1" - [(set_attr "neon_type" "neon_shift_1")] + [(set_attr "type" "neon_shift_1")] ) (define_expand "vec_pack_trunc_" @@ -5955,7 +5954,7 @@ (define_insn "neon_vabd_2" (match_operand:VDQ 2 "s_register_operand" "w"))))] "TARGET_NEON && (! || flag_unsafe_math_optimizations)" "vabd. %0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (ne (symbol_ref "") (const_int 0)) (if_then_else (ne (symbol_ref "") (const_int 0)) (const_string "neon_fp_vadd_ddd_vabs_dd") @@ -5970,7 +5969,7 @@ (define_insn "neon_vabd_3" UNSPEC_VSUB)))] "TARGET_NEON && (! || flag_unsafe_math_optimizations)" "vabd. %0, %1, %2" - [(set (attr "neon_type") + [(set (attr "type") (if_then_else (ne (symbol_ref "") (const_int 0)) (if_then_else (ne (symbol_ref "") (const_int 0)) (const_string "neon_fp_vadd_ddd_vabs_dd") diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index 51dbc7c37d72d71b483af70d4fbaf71a7cd36b7f..1b7db65f2282fd7aadb8664b27dc107d9159a9bb 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -39,11 +39,14 @@ ; call subroutine call. ; clz count leading zeros (CLZ). ; extend extend instruction (SXTB, SXTH, UXTB, UXTH). -; f_2_r transfer from float to core (no memory needed). ; f_cvt conversion between float and integral. ; f_flag transfer of co-processor flags to the CPSR. ; f_load[d,s] double/single load from memory. Used for VFP unit. +; f_mcr transfer arm to vfp reg. +; f_mcrr transfer two arm regs to vfp reg. ; f_minmax[d,s] double/single floating point minimum/maximum. +; f_mrc transfer vfp to arm reg. +; f_mrrc transfer vfp to two arm regs. ; f_rint[d,s] double/single floating point rount to integral. ; f_sel[d,s] double/single floating byte select. ; f_store[d,s] double/single store to memory. Used for VFP unit. @@ -77,7 +80,6 @@ ; mvn_reg inverting move instruction, register. ; mvn_shift inverting move instruction, shifted operand by a constant. ; mvn_shift_reg inverting move instruction, shifted operand by a register. -; r_2_f transfer from core to float. ; sdiv signed division. ; shift simple shift operation (LSL, LSR, ASR, ROR) with an ; immediate. @@ -181,6 +183,71 @@ ; wmmx_wunpckih ; wmmx_wunpckil ; wmmx_wxor +; +; The classification below is for NEON instructions. +; +; neon_bp_2cycle +; neon_bp_3cycle +; neon_bp_simple +; neon_fp_vadd_ddd_vabs_dd +; neon_fp_vadd_qqq_vabs_qq +; neon_fp_vmla_ddd_scalar +; neon_fp_vmla_ddd +; neon_fp_vmla_qqq_scalar +; neon_fp_vmla_qqq +; neon_fp_vmul_ddd +; neon_fp_vmul_qqd +; neon_fp_vrecps_vrsqrts_ddd +; neon_fp_vrecps_vrsqrts_qqq +; neon_fp_vsum +; neon_int_1 +; neon_int_2 +; neon_int_3 +; neon_int_4 +; neon_int_5 +; neon_ldm_2 +; neon_ldr +; neon_mcr_2_mcrr +; neon_mcr +; neon_mla_ddd_16_scalar_qdd_32_16_long_scalar +; neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long +; neon_mla_ddd_8_16_qdd_16_8_long_32_16_long +; neon_mla_qqq_32_qqd_32_scalar +; neon_mla_qqq_8_16 +; neon_mrc +; neon_mrrc +; neon_mul_ddd_16_scalar_32_16_long_scalar +; neon_mul_ddd_8_16_qdd_16_8_long_32_16_long +; neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar +; neon_mul_qqd_32_scalar +; neon_mul_qqq_8_16_32_ddd_32 +; neon_shift_1 +; neon_shift_2 +; neon_shift_3 +; neon_stm_2 +; neon_str +; neon_vaba_qqq +; neon_vaba +; neon_vld1_1_2_regs +; neon_vld1_3_4_regs +; neon_vld1_vld2_lane +; neon_vld2_2_regs_vld1_vld2_all_lanes +; neon_vld2_4_regs +; neon_vld3_vld4_all_lanes +; neon_vld3_vld4_lane +; neon_vld3_vld4 +; neon_vmov +; neon_vqneg_vqabs +; neon_vqshl_vrshl_vqrshl_qqq +; neon_vshl_ddd +; neon_vsma +; neon_vsra_vrsra +; neon_vst1_1_2_regs_vst2_2_regs +; neon_vst1_3_4_regs +; neon_vst1_vst2_lane +; neon_vst2_4_regs_vst3_vst4 +; neon_vst3_vst4_lane +; neon_vst3_vst4 (define_attr "type" "arlo_imm,\ @@ -192,13 +259,16 @@ (define_attr "type" call,\ clz,\ extend,\ - f_2_r,\ f_cvt,\ f_flag,\ f_loadd,\ f_loads,\ + f_mcr,\ + f_mcrr,\ f_minmaxd,\ f_minmaxs,\ + f_mrc,\ + f_mrrc,\ f_rintd,\ f_rints,\ f_seld,\ @@ -241,7 +311,6 @@ (define_attr "type" mvn_reg,\ mvn_shift,\ mvn_shift_reg,\ - r_2_f,\ sdiv,\ shift,\ shift_reg,\ @@ -337,8 +406,70 @@ (define_attr "type" wmmx_wunpckel,\ wmmx_wunpckih,\ wmmx_wunpckil,\ - wmmx_wxor" - (const_string "arlo_reg")) + wmmx_wxor,\ + neon_bp_2cycle,\ + neon_bp_3cycle,\ + neon_bp_simple,\ + neon_fp_vadd_ddd_vabs_dd,\ + neon_fp_vadd_qqq_vabs_qq,\ + neon_fp_vmla_ddd_scalar,\ + neon_fp_vmla_ddd,\ + neon_fp_vmla_qqq_scalar,\ + neon_fp_vmla_qqq,\ + neon_fp_vmul_ddd,\ + neon_fp_vmul_qqd,\ + neon_fp_vrecps_vrsqrts_ddd,\ + neon_fp_vrecps_vrsqrts_qqq,\ + neon_fp_vsum,\ + neon_int_1,\ + neon_int_2,\ + neon_int_3,\ + neon_int_4,\ + neon_int_5,\ + neon_ldm_2,\ + neon_ldr,\ + neon_mcr_2_mcrr,\ + neon_mcr,\ + neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\ + neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\ + neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ + neon_mla_qqq_32_qqd_32_scalar,\ + neon_mla_qqq_8_16,\ + neon_mrc,\ + neon_mrrc,\ + neon_mul_ddd_16_scalar_32_16_long_scalar,\ + neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ + neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\ + neon_mul_qqd_32_scalar,\ + neon_mul_qqq_8_16_32_ddd_32,\ + neon_shift_1,\ + neon_shift_2,\ + neon_shift_3,\ + neon_stm_2,\ + neon_str,\ + neon_vaba_qqq,\ + neon_vaba,\ + neon_vld1_1_2_regs,\ + neon_vld1_3_4_regs,\ + neon_vld1_vld2_lane,\ + neon_vld2_2_regs_vld1_vld2_all_lanes,\ + neon_vld2_4_regs,\ + neon_vld3_vld4_all_lanes,\ + neon_vld3_vld4_lane,\ + neon_vld3_vld4,\ + neon_vmov,\ + neon_vqneg_vqabs,\ + neon_vqshl_vrshl_vqrshl_qqq,\ + neon_vshl_ddd,\ + neon_vsma,\ + neon_vsra_vrsra,\ + neon_vst1_1_2_regs_vst2_2_regs,\ + neon_vst1_3_4_regs,\ + neon_vst1_vst2_lane,\ + neon_vst2_4_regs_vst3_vst4,\ + neon_vst3_vst4_lane,\ + neon_vst3_vst4" + (const_string "arlo_reg")) ; Is this an (integer side) multiply with a 32-bit (or smaller) result? (define_attr "mul32" "no,yes" diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index ef8777a900bfdc539b3d688665d815e61873f693..ea4c1f5834f58dec855979420a8d701d8273ee53 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -53,8 +53,7 @@ (define_insn "*arm_movsi_vfp" } " [(set_attr "predicable" "yes") - (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") - (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") + (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,f_mcr,f_mrc,fcpys,f_loads,f_stores") (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] ) @@ -101,9 +100,8 @@ (define_insn "*thumb2_movsi_vfp" " [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no") - (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_reg,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") + (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_reg,load1,load1,store1,store1,f_mcr,f_mrc,fcpys,f_loads,f_stores") (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4") - (set_attr "neon_type" "*,*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*") (set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] ) @@ -146,8 +144,7 @@ (define_insn "*movdi_vfp" gcc_unreachable (); } " - [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") - (set_attr "neon_type" "*,*,*,*,*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*") + [(set_attr "type" "*,*,*,*,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored") (set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8) (eq_attr "alternative" "2") (const_int 12) (eq_attr "alternative" "3") (const_int 16) @@ -195,8 +192,7 @@ (define_insn "*movdi_vfp_cortexa8" gcc_unreachable (); } " - [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") - (set_attr "neon_type" "*,*,*,*,*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*") + [(set_attr "type" "*,*,*,*,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored") (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8) (eq_attr "alternative" "2") (const_int 12) (eq_attr "alternative" "3") (const_int 16) @@ -264,8 +260,8 @@ (define_insn "*movhf_vfp_neon" } " [(set_attr "conds" "unconditional") - (set_attr "type" "*,*,load1,store1,fcpys,*,r_2_f,f_2_r,*") - (set_attr "neon_type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,*,*,*,*,*,*,*") + (set_attr "type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,\ + load1,store1,fcpys,*,f_mcr,f_mrc,*") (set_attr "length" "4,4,4,4,4,4,4,4,8")] ) @@ -315,7 +311,7 @@ (define_insn "*movhf_vfp" } " [(set_attr "conds" "unconditional") - (set_attr "type" "load1,store1,fcpys,*,r_2_f,f_2_r,*") + (set_attr "type" "load1,store1,fcpys,*,f_mcr,f_mrc,*") (set_attr "length" "4,4,4,4,4,4,8")] ) @@ -355,8 +351,7 @@ (define_insn "*movsf_vfp" " [(set_attr "predicable" "yes") (set_attr "type" - "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg") - (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*") + "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg") (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*") (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")] ) @@ -393,8 +388,7 @@ (define_insn "*thumb2_movsf_vfp" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" - "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg") - (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*") + "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg") (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*") (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] ) @@ -434,9 +428,8 @@ (define_insn "*movdf_vfp" } } " - [(set_attr "type" - "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*") - (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*") + [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_stored,\ + load2,store2,ffarithd,*") (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8) (eq_attr "alternative" "7") (if_then_else @@ -480,9 +473,8 @@ (define_insn "*thumb2_movdf_vfp" } } " - [(set_attr "type" - "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*") - (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*") + [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,\ + f_stored,load2,store2,ffarithd,*") (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8) (eq_attr "alternative" "7") (if_then_else @@ -517,8 +509,7 @@ (define_insn "*movsfcc_vfp" fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" [(set_attr "conds" "use") (set_attr "length" "4,4,8,4,4,8,4,4,8") - (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") - (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")] + (set_attr "type" "fcpys,fcpys,fcpys,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")] ) (define_insn "*thumb2_movsfcc_vfp" @@ -541,8 +532,7 @@ (define_insn "*thumb2_movsfcc_vfp" ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" [(set_attr "conds" "use") (set_attr "length" "6,6,10,6,6,10,6,6,10") - (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") - (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")] + (set_attr "type" "fcpys,fcpys,fcpys,f_mcr,f_mcr,f_mcr,f_mrc,f_mrc,f_mrc")] ) (define_insn "*movdfcc_vfp" @@ -565,8 +555,7 @@ (define_insn "*movdfcc_vfp" fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" [(set_attr "conds" "use") (set_attr "length" "4,4,8,4,4,8,4,4,8") - (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") - (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")] + (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")] ) (define_insn "*thumb2_movdfcc_vfp" @@ -589,8 +578,7 @@ (define_insn "*thumb2_movdfcc_vfp" ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" [(set_attr "conds" "use") (set_attr "length" "6,6,10,6,6,10,6,6,10") - (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") - (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")] + (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")] ) diff --git a/gcc/config/arm/vfp11.md b/gcc/config/arm/vfp11.md index b027fe6c3cd30c1e51fb4dbead2282d95a19e9c7..9e6ba849a718c7577006d9aad545fd26b0392107 100644 --- a/gcc/config/arm/vfp11.md +++ b/gcc/config/arm/vfp11.md @@ -77,12 +77,12 @@ (define_insn_reservation "vfp_fdivd" 33 ;; Moves to/from arm regs also use the load/store pipeline. (define_insn_reservation "vfp_fload" 4 (and (eq_attr "generic_vfp" "yes") - (eq_attr "type" "f_loads,f_loadd,r_2_f")) + (eq_attr "type" "f_loads,f_loadd,f_mcr,f_mcrr")) "vfp_ls") (define_insn_reservation "vfp_fstore" 4 (and (eq_attr "generic_vfp" "yes") - (eq_attr "type" "f_stores,f_stored,f_2_r")) + (eq_attr "type" "f_stores,f_stored,f_mrc,f_mrrc")) "vfp_ls") (define_insn_reservation "vfp_to_cpsr" 4 diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index c6664fa..04f76fe 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -9651,7 +9651,7 @@ Here's an example of int iterators in action, taken from the ARM port: QABSNEG))] "TARGET_NEON" "vq.\t%0, %1" - [(set_attr "neon_type" "neon_vqneg_vqabs")] + [(set_attr "type" "neon_vqneg_vqabs")] ) @end smallexample @@ -9666,7 +9666,7 @@ This is equivalent to: UNSPEC_VQABS))] "TARGET_NEON" "vqabs.\t%0, %1" - [(set_attr "neon_type" "neon_vqneg_vqabs")] + [(set_attr "type" "neon_vqneg_vqabs")] ) (define_insn "neon_vqneg" @@ -9676,7 +9676,7 @@ This is equivalent to: UNSPEC_VQNEG))] "TARGET_NEON" "vqneg.\t%0, %1" - [(set_attr "neon_type" "neon_vqneg_vqabs")] + [(set_attr "type" "neon_vqneg_vqabs")] ) @end smallexample --------------1.8.3-rc0--