From patchwork Tue Jun 18 15:42:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julian Brown X-Patchwork-Id: 252376 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 935382C0299 for ; Wed, 19 Jun 2013 01:42:55 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; q=dns; s= default; b=WnnsBhGLvepezGf0TOx03M56I5xHEMVLudU0fDQHDZvQFeRCF2F5/ gUkdUqafjZjrz5XLPKiGm3IO3IHHufVPIU+aWhUDJkwlYDvGzx6TNaHVlx2Yk6TV tQb/H/WziAYdKHD92Hg2G3w3m2oIwnEnhQan6sG0amiNffqTlrhpYQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; s= default; bh=tVvHEUCqUUnnwybGxuWZ3/aynDo=; b=LhSoylH2qWIXNgdCVfSm gjFYHrRHtqvKv2xmvvj2ODssb41KcNXbo2zUhIo45qWkfHiRJKnu5JFLVyUugLbc 8YjnANpIJHY3b0VfJqB86bHqlFoHw4aYVxTf3ba+4GwFDLQa6Rtw0CQd9KTyZVcX pyfU8NaZhCoi1KqhZX+21oA= Received: (qmail 5962 invoked by alias); 18 Jun 2013 15:42:47 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5952 invoked by uid 89); 18 Jun 2013 15:42:46 -0000 X-Spam-SWARE-Status: No, score=-3.7 required=5.0 tests=AWL, BAYES_00, FROM_12LTRDOM, KHOP_RCVD_UNTRUST, RCVD_IN_HOSTKARMA_W, RCVD_IN_HOSTKARMA_WL autolearn=no version=3.3.1 Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Tue, 18 Jun 2013 15:42:40 +0000 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1Uoy3K-0000g5-Ir from Julian_Brown@mentor.com ; Tue, 18 Jun 2013 08:42:38 -0700 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 18 Jun 2013 08:42:38 -0700 Received: from octopus (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.2.247.3; Tue, 18 Jun 2013 16:42:36 +0100 Date: Tue, 18 Jun 2013 16:42:13 +0100 From: Julian Brown To: , Richard Earnshaw , Ramana Radhakrishnan Subject: [PATCH, ARM] Reintroduce minipool ranges for zero-extension insn patterns Message-ID: <20130618164213.73dbf8c2@octopus> MIME-Version: 1.0 X-Virus-Found: No Hi, The following patch removed pool_range/neg_pool_range attributes from several instructions as a cleanup, which I believe to have been incorrect: http://gcc.gnu.org/ml/gcc-patches/2010-07/msg01036.html On a Mentor-local branch, this caused problems with instructions like: (insn 77 53 87 (set (reg:SI 8 r8 [orig:197 s.4 ] [197]) (zero_extend:SI (mem/u/c:HI (symbol_ref/u:SI ("*.LC0") [flags 0x2]) [7 S2 A16]))) [...] 161 {*arm_zero_extendhisi2_v6} (nil)) The reasoning behind the cleanup was that the instructions in question have no immediate constraints -- but the minipool code is used for more than just immediates, e.g. in the above case where a symbol reference ("m") is loaded. I don't have a test case for the problem on mainline at present, but I believe it is still a latent bug. Tested with the default multilibs (ARM & Thumb mode) on arm-none-eabi, with no regressions. (The patch has also been tested with more multilibs on our local branches for a while, and I did ensure previously that it did not adversely affect Bernd's patch linked above.) OK to apply? Thanks, Julian ChangeLog gcc/ * arm.md (*thumb1_zero_extendhisi2, *arm_zero_extendhisi2) (*arm_zero_extendhisi2_v6, *thumb1_zero_extendqisi2) (*thumb1_zero_extendqisi2_v6, *arm_zero_extendqisi2) (*arm_zero_extendqisi2_v6): Add pool_range, neg_pool_range attributes. Index: gcc/config/arm/arm.md =================================================================== --- gcc/config/arm/arm.md (revision 200171) +++ gcc/config/arm/arm.md (working copy) @@ -5313,7 +5313,8 @@ [(if_then_else (eq_attr "is_arch6" "yes") (const_int 2) (const_int 4)) (const_int 4)]) - (set_attr "type" "simple_alu_shift, load_byte")] + (set_attr "type" "simple_alu_shift, load_byte") + (set_attr "pool_range" "*,60")] ) (define_insn "*arm_zero_extendhisi2" @@ -5324,7 +5325,9 @@ # ldr%(h%)\\t%0, %1" [(set_attr "type" "alu_shift,load_byte") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,256") + (set_attr "neg_pool_range" "*,244")] ) (define_insn "*arm_zero_extendhisi2_v6" @@ -5335,7 +5338,9 @@ uxth%?\\t%0, %1 ldr%(h%)\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "type" "simple_alu_shift,load_byte")] + (set_attr "type" "simple_alu_shift,load_byte") + (set_attr "pool_range" "*,256") + (set_attr "neg_pool_range" "*,244")] ) (define_insn "*arm_zero_extendhisi2addsi" @@ -5405,7 +5410,8 @@ uxtb\\t%0, %1 ldrb\\t%0, %1" [(set_attr "length" "2") - (set_attr "type" "simple_alu_shift,load_byte")] + (set_attr "type" "simple_alu_shift,load_byte") + (set_attr "pool_range" "*,32")] ) (define_insn "*arm_zero_extendqisi2" @@ -5417,7 +5423,9 @@ ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" [(set_attr "length" "8,4") (set_attr "type" "alu_shift,load_byte") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,4096") + (set_attr "neg_pool_range" "*,4084")] ) (define_insn "*arm_zero_extendqisi2_v6" @@ -5428,7 +5436,9 @@ uxtb%(%)\\t%0, %1 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" [(set_attr "type" "simple_alu_shift,load_byte") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,4096") + (set_attr "neg_pool_range" "*,4084")] ) (define_insn "*arm_zero_extendqisi2addsi"