From patchwork Mon Oct 3 00:50:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Miller X-Patchwork-Id: 117383 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 018F7B6F75 for ; Mon, 3 Oct 2011 11:50:47 +1100 (EST) Received: (qmail 19002 invoked by alias); 3 Oct 2011 00:50:43 -0000 Received: (qmail 18992 invoked by uid 22791); 3 Oct 2011 00:50:40 -0000 X-SWARE-Spam-Status: No, hits=-1.7 required=5.0 tests=AWL,BAYES_00,TW_SV X-Spam-Check-By: sourceware.org Received: from shards.monkeyblade.net (HELO shards.monkeyblade.net) (198.137.202.13) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 03 Oct 2011 00:50:25 +0000 Received: from localhost (cpe-66-65-62-183.nyc.res.rr.com [66.65.62.183]) (authenticated bits=0) by shards.monkeyblade.net (8.14.4/8.14.4) with ESMTP id p930oNDW017204 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 2 Oct 2011 17:50:23 -0700 Date: Sun, 02 Oct 2011 20:50:22 -0400 (EDT) Message-Id: <20111002.205022.545130502753260605.davem@davemloft.net> To: gcc-patches@gcc.gnu.org CC: rth@redhat.com Subject: [PATCH] Add missing sparc shift zero extensions, and fix shift attributes. From: David Miller Mime-Version: 1.0 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This is a patch Richard came up with earlier this year when I had him look into some excessive sign/zero extensions the compiler was making on sparc 64-bit. I finally got around to validating this patch and while doing so noticed that we've had the instruction attributes screwed up on shifts for quite some time. A very long time ago, we used to amit "add x, x, y" for a constant shift left of one. But that hack got removed a long time, but when it got removed the conditional attribute setting was left around. Committed to trunk. gcc/ * config/sparc/sparc.md (ashlsi3, *ashldi3_sp64): Remove conditional insn type setting, we always emit a shift. (*ashlsi3_extend, *lshrsi3_extend0): New patterns. (*lshrsi3_extend): Rename to *lshrsi3_extend1. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@179441 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 8 ++++++++ gcc/config/sparc/predicates.md | 5 ----- gcc/config/sparc/sparc.md | 36 +++++++++++++++++++++++++++++------- 3 files changed, 37 insertions(+), 12 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0f32049..fbc0b20 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2011-10-02 Richard Henderson + David S. Miller + + * config/sparc/sparc.md (ashlsi3, *ashldi3_sp64): Remove + conditional insn type setting, we always emit a shift. + (*ashlsi3_extend, *lshrsi3_extend0): New patterns. + (*lshrsi3_extend): Rename to *lshrsi3_extend1. + 2011-10-02 Gerald Pfeifer * invoke.texi (SPARC Options): Refer to GNU/Linux. diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md index 21399b5..f0be149 100644 --- a/gcc/config/sparc/predicates.md +++ b/gcc/config/sparc/predicates.md @@ -24,11 +24,6 @@ (and (match_code "const_int,const_double,const_vector") (match_test "op == CONST0_RTX (mode)"))) -;; Return true if OP is the one constant for MODE. -(define_predicate "const_one_operand" - (and (match_code "const_int,const_double,const_vector") - (match_test "op == CONST1_RTX (mode)"))) - ;; Return true if the integer representation of OP is ;; all-ones. (define_predicate "const_all_ones_operand" diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 03158c7..6990746 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -5814,9 +5814,20 @@ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); return "sll\t%1, %2, %0"; } - [(set (attr "type") - (if_then_else (match_operand 2 "const_one_operand" "") - (const_string "ialu") (const_string "shift")))]) + [(set_attr "type" "shift")]) + +(define_insn "*ashlsi3_extend" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (ashift:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "rI"))))] + "TARGET_ARCH64" +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + return "sll\t%1, %2, %0"; +} + [(set_attr "type" "shift")]) (define_expand "ashldi3" [(set (match_operand:DI 0 "register_operand" "=r") @@ -5843,9 +5854,7 @@ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); return "sllx\t%1, %2, %0"; } - [(set (attr "type") - (if_then_else (match_operand 2 "const_one_operand" "") - (const_string "ialu") (const_string "shift")))]) + [(set_attr "type" "shift")]) ;; XXX UGH! (define_insn "ashldi3_v8plus" @@ -5980,10 +5989,23 @@ } [(set_attr "type" "shift")]) +(define_insn "*lshrsi3_extend0" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "rI"))))] + "TARGET_ARCH64" + { + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + return "srl\t%1, %2, %0"; + } + [(set_attr "type" "shift")]) + ;; This handles the case where ;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))), ;; but combiner "simplifies" it for us. -(define_insn "*lshrsi3_extend" +(define_insn "*lshrsi3_extend1" [(set (match_operand:DI 0 "register_operand" "=r") (and:DI (subreg:DI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "r")) 0)