From patchwork Mon Sep 26 21:11:27 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Miller X-Patchwork-Id: 116482 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 5A14BB6F6F for ; Tue, 27 Sep 2011 07:11:47 +1000 (EST) Received: (qmail 17015 invoked by alias); 26 Sep 2011 21:11:44 -0000 Received: (qmail 17007 invoked by uid 22791); 26 Sep 2011 21:11:43 -0000 X-SWARE-Spam-Status: No, hits=-1.6 required=5.0 tests=AWL,BAYES_00,TW_FC X-Spam-Check-By: sourceware.org Received: from shards.monkeyblade.net (HELO shards.monkeyblade.net) (198.137.202.13) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 26 Sep 2011 21:11:29 +0000 Received: from localhost (cpe-66-65-62-183.nyc.res.rr.com [66.65.62.183]) (authenticated bits=0) by shards.monkeyblade.net (8.14.4/8.14.4) with ESMTP id p8QLBRed027491 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 26 Sep 2011 14:11:28 -0700 Date: Mon, 26 Sep 2011 17:11:27 -0400 (EDT) Message-Id: <20110926.171127.956076333441810249.davem@davemloft.net> To: gcc-patches@gcc.gnu.org Subject: [PATCH] Add rdgsr, edge, and pixel-compare VIS tests. From: David Miller Mime-Version: 1.0 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Committed to trunk. gcc/testsuite/ * gcc.target/sparc/rdgsr.c: New test. * gcc.target/sparc/edge.c: New test. * gcc.target/sparc/fcmp.c: New test. --- gcc/testsuite/ChangeLog | 3 ++ gcc/testsuite/gcc.target/sparc/edge.c | 39 +++++++++++++++++++++++ gcc/testsuite/gcc.target/sparc/fcmp.c | 53 ++++++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/sparc/rdgsr.c | 9 +++++ 4 files changed, 104 insertions(+), 0 deletions(-) create mode 100644 gcc/testsuite/gcc.target/sparc/edge.c create mode 100644 gcc/testsuite/gcc.target/sparc/fcmp.c create mode 100644 gcc/testsuite/gcc.target/sparc/rdgsr.c diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c8619b8..1447608 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,6 +1,9 @@ 2011-09-26 David S. Miller * gcc.target/sparc/wrgsr.c: New test. + * gcc.target/sparc/rdgsr.c: New test. + * gcc.target/sparc/edge.c: New test. + * gcc.target/sparc/fcmp.c: New test. 2011-09-26 Janus Weil diff --git a/gcc/testsuite/gcc.target/sparc/edge.c b/gcc/testsuite/gcc.target/sparc/edge.c new file mode 100644 index 0000000..fcd7104 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/edge.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mcpu=ultrasparc -mvis" } */ + +int test_edge8 (void *p1, void *p2) +{ + return __builtin_vis_edge8 (p1, p2); +} + +int test_edge8l (void *p1, void *p2) +{ + return __builtin_vis_edge8l (p1, p2); +} + +int test_edge16 (void *p1, void *p2) +{ + return __builtin_vis_edge16 (p1, p2); +} + +int test_edge16l (void *p1, void *p2) +{ + return __builtin_vis_edge16l (p1, p2); +} + +int test_edge32 (void *p1, void *p2) +{ + return __builtin_vis_edge32 (p1, p2); +} + +int test_edge32l (void *p1, void *p2) +{ + return __builtin_vis_edge32l (p1, p2); +} + +/* { dg-final { scan-assembler "edge8\t%" } } */ +/* { dg-final { scan-assembler "edge8l\t%" } } */ +/* { dg-final { scan-assembler "edge16\t%" } } */ +/* { dg-final { scan-assembler "edge16l\t%" } } */ +/* { dg-final { scan-assembler "edge32\t%" } } */ +/* { dg-final { scan-assembler "edge32l\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fcmp.c b/gcc/testsuite/gcc.target/sparc/fcmp.c new file mode 100644 index 0000000..42b5bdc --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fcmp.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=ultrasparc -mvis" } */ +typedef int vec32 __attribute__((vector_size(8))); +typedef short vec16 __attribute__((vector_size(8))); + +int test_fcmple16 (vec16 a, vec16 b) +{ + return __builtin_vis_fcmple16 (a, b); +} + +int test_fcmple32 (vec32 a, vec32 b) +{ + return __builtin_vis_fcmple32 (a, b); +} + +int test_fcmpne16 (vec16 a, vec16 b) +{ + return __builtin_vis_fcmpne16 (a, b); +} + +int test_fcmpne32 (vec32 a, vec32 b) +{ + return __builtin_vis_fcmpne32 (a, b); +} + +int test_fcmpgt16 (vec16 a, vec16 b) +{ + return __builtin_vis_fcmpgt16 (a, b); +} + +int test_fcmpgt32 (vec32 a, vec32 b) +{ + return __builtin_vis_fcmpgt32 (a, b); +} + +int test_fcmpeq16 (vec16 a, vec16 b) +{ + return __builtin_vis_fcmpeq16 (a, b); +} + +int test_fcmpeq32 (vec32 a, vec32 b) +{ + return __builtin_vis_fcmpeq32 (a, b); +} + +/* { dg-final { scan-assembler "fcmple16\t%" } } */ +/* { dg-final { scan-assembler "fcmple32\t%" } } */ +/* { dg-final { scan-assembler "fcmpne16\t%" } } */ +/* { dg-final { scan-assembler "fcmpne32\t%" } } */ +/* { dg-final { scan-assembler "fcmpgt16\t%" } } */ +/* { dg-final { scan-assembler "fcmpgt32\t%" } } */ +/* { dg-final { scan-assembler "fcmpeq16\t%" } } */ +/* { dg-final { scan-assembler "fcmpeq32\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/rdgsr.c b/gcc/testsuite/gcc.target/sparc/rdgsr.c new file mode 100644 index 0000000..e67bdac --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/rdgsr.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mcpu=ultrasparc -mvis" } */ + +long get_gsr (void) +{ + return __builtin_vis_read_gsr (); +} + +/* { dg-final { scan-assembler "rd\t%gsr" } } */