===================================================================
@@ -4482,17 +4482,20 @@ m32c_emit_prologue (void)
/* Likewise, for the epilogue. The only exception is that, for
interrupts, we must manually unwind the frame as the REIT opcode
doesn't do that. */
void
m32c_emit_epilogue (void)
{
+ int popm_count = m32c_pushm_popm (PP_justcount);
+
/* This just emits a comment into the .s file for debugging. */
- if (m32c_pushm_popm (PP_justcount) > 0 || cfun->machine->is_interrupt)
+ if (popm_count > 0 || cfun->machine->is_interrupt)
emit_insn (gen_epilogue_start ());
- m32c_pushm_popm (PP_popm);
+ if (popm_count > 0)
+ m32c_pushm_popm (PP_popm);
if (cfun->machine->is_interrupt)
{
enum machine_mode spmode = TARGET_A16 ? HImode : PSImode;
/* REIT clears B flag and restores $fp for us, but we still
@@ -4543,25 +4546,23 @@ m32c_emit_epilogue (void)
else if (cfun->machine->use_rts)
emit_jump_insn (gen_epilogue_rts ());
else if (TARGET_A16)
emit_jump_insn (gen_epilogue_exitd_16 ());
else
emit_jump_insn (gen_epilogue_exitd_24 ());
- emit_barrier ();
}
void
m32c_emit_eh_epilogue (rtx ret_addr)
{
/* R0[R2] has the stack adjustment. R1[R3] has the address to
return to. We have to fudge the stack, pop everything, pop SP
(fudged), and return (fudged). This is actually easier to do in
assembler, so punt to libgcc. */
emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));
/* emit_clobber (gen_rtx_REG (HImode, R0L_REGNO)); */
- emit_barrier ();
}
/* Indicate which flags must be properly set for a given conditional. */
static int
flags_needed_for_conditional (rtx cond)
{
===================================================================
@@ -212,14 +212,14 @@
;; 0 = target: set to &NUL in dest
;; 1 = destination (mem:BLK ...)
;; 2 = source (mem:BLK ...)
(define_expand "movstr"
[(match_operand 0 "m32c_nonimmediate_operand" "")
- (match_operand 1 "ap_operand" "")
- (match_operand 2 "ap_operand" "")
+ (match_operand 1 "" "")
+ (match_operand 2 "" "")
]
"TARGET_A24"
"if (m32c_expand_movstr(operands)) DONE; FAIL;"
)
;; 0 = dest (out)
===================================================================
@@ -198,13 +198,13 @@ machine_function;
#define SIZE_TYPE "unsigned int"
#undef WCHAR_TYPE
#define WCHAR_TYPE "long int"
#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
+#define WCHAR_TYPE_SIZE 32
/* REGISTER USAGE */
/* Register Basics */
/* Register layout:
@@ -285,38 +285,39 @@ machine_function;
{ 0x00000004 }, /* R1 - r1 */\
{ 0x00000002 }, /* R2 - r2 */\
{ 0x00000008 }, /* R3 - r3 */\
{ 0x00000003 }, /* R02 - r0r2 */\
{ 0x0000000c }, /* R13 - r1r3 */\
{ 0x00000005 }, /* HL - r0 r1 */\
- { 0x00000005 }, /* QI - r0 r1 */\
{ 0x0000000a }, /* R23 - r2 r3 */\
{ 0x0000000f }, /* R03 - r0r2 r1r3 */\
- { 0x0000000f }, /* DI - r0r2r1r3 + mems */\
{ 0x00000010 }, /* A0 - a0 */\
{ 0x00000020 }, /* A1 - a1 */\
{ 0x00000030 }, /* A - a0 a1 */\
{ 0x000000f0 }, /* AD - a0 a1 sb fp */\
{ 0x000001f0 }, /* PS - a0 a1 sb fp sp */\
- { 0x0000000f }, /* SI - r0r2 r1r3 a0a1 */\
- { 0x0000003f }, /* HI - r0 r1 r2 r3 a0 a1 */\
{ 0x00000033 }, /* R02A - r0r2 a0 a1 */ \
- { 0x0000003f }, /* RA - r0..r3 a0 a1 */\
+ { 0x0000003f }, /* RA - r0 r1 r2 r3 a0 a1 */\
{ 0x0000007f }, /* GENERAL */\
{ 0x00000400 }, /* FLG */\
{ 0x000001ff }, /* HC - r0l r1 r2 r3 a0 a1 sb fb sp */\
{ 0x000ff000 }, /* MEM */\
{ 0x000ff003 }, /* R02_A_MEM */\
{ 0x000ff005 }, /* A_HL_MEM */\
{ 0x000ff00c }, /* R1_R3_A_MEM */\
{ 0x000ff00f }, /* R03_MEM */\
{ 0x000ff03f }, /* A_HI_MEM */\
{ 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
- { 0x000ff1ff }, /* ALL */\
+ { 0x000ff5ff }, /* ALL */\
}
+#define QI_REGS HL_REGS
+#define HI_REGS RA_REGS
+#define SI_REGS R03_REGS
+#define DI_REGS R03_REGS
+
enum reg_class
{
NO_REGS,
SP_REGS,
FB_REGS,
SB_REGS,
@@ -325,23 +326,19 @@ enum reg_class
R1_REGS,
R2_REGS,
R3_REGS,
R02_REGS,
R13_REGS,
HL_REGS,
- QI_REGS,
R23_REGS,
R03_REGS,
- DI_REGS,
A0_REGS,
A1_REGS,
A_REGS,
AD_REGS,
PS_REGS,
- SI_REGS,
- HI_REGS,
R02A_REGS,
RA_REGS,
GENERAL_REGS,
FLG_REGS,
HC_REGS,
MEM_REGS,
@@ -367,23 +364,19 @@ enum reg_class
"R1_REGS", \
"R2_REGS", \
"R3_REGS", \
"R02_REGS", \
"R13_REGS", \
"HL_REGS", \
-"QI_REGS", \
"R23_REGS", \
"R03_REGS", \
-"DI_REGS", \
"A0_REGS", \
"A1_REGS", \
"A_REGS", \
"AD_REGS", \
"PS_REGS", \
-"SI_REGS", \
-"HI_REGS", \
"R02A_REGS", \
"RA_REGS", \
"GENERAL_REGS", \
"FLG_REGS", \
"HC_REGS", \
"MEM_REGS", \
===================================================================
@@ -85,20 +85,23 @@
"m32c_emit_epilogue(); DONE;"
)
(define_expand "eh_return"
[(match_operand:PSI 0 "" "")]
""
- "m32c_emit_eh_epilogue(operands[0]); DONE;"
+ "m32c_emit_eh_epilogue(operands[0]);
+ emit_barrier ();
+ DONE;"
)
(define_insn "eh_epilogue"
[(set (pc)
(unspec_volatile [(match_operand 0 "m32c_r1_operand" "")
(match_operand 1 "m32c_r0_operand" "")
- ] UNS_EH_EPILOGUE))]
+ ] UNS_EH_EPILOGUE))
+ (return)]
""
"jmp.a\t__m32c_eh_return"
[(set_attr "flags" "x")]
)
(define_insn "epilogue_exitd_16"