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PR 47580: Fix corner case on powerpc using --with-cpu=power7

Message ID 20110202011359.GA23486@hungry-tiger.westford.ibm.com
State New
Headers show

Commit Message

Michael Meissner Feb. 2, 2011, 1:13 a.m. UTC 
There were still some corner cases, notably:
gcc/testsuite/gcc.c-torture/execute/20050121-1.c

While the right solution is to tighten the predicates in general, so that we
don't get inappropriate hard/virtual registers generated early, I decided that
for GCC 4.6, it is better just to make the VSX insns use the same predicate as
the expanders.  I had started patches to do use more specific predicates, but
it was too complex for this stage of the release cycle.  This patch fixes both
the original problem that the earlier one did as well as 20050121-1.c.

I have done a bootstrap using --with-cpu=power7 and make check, and there were
no regressions other than the other --with-cpu=power7 that are not related to
this patch:
	gcc.dg/pr42461.c		(Peter Bergner has a fix)
	gcc.dg/stack-usage-1.c		(patch submitted)
	gcc.dg/sms-3.c			(unknown)

Is it ok to install the patch?

2011-02-01  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/47580
	* config/rs6000/vsx.md (vsx_float<VSi><mode>2): Use
	gpc_reg_operand instead of vsx_register_operand to match rs6000.md
	generator functions.
	(vsx_floatuns<VSi><mode>2): Ditto.
	(vsx_fix_trunc<mode><VSi>2): Ditto.
	(vsx_fixuns_trunc<mode><VSi>2): Ditto.

Comments

David Edelsohn Feb. 2, 2011, 9:29 p.m. UTC | #1 
On Tue, Feb 1, 2011 at 8:13 PM, Michael Meissner
<meissner@linux.vnet.ibm.com> wrote:
> There were still some corner cases, notably:
> gcc/testsuite/gcc.c-torture/execute/20050121-1.c
>
> While the right solution is to tighten the predicates in general, so that we
> don't get inappropriate hard/virtual registers generated early, I decided that
> for GCC 4.6, it is better just to make the VSX insns use the same predicate as
> the expanders.  I had started patches to do use more specific predicates, but
> it was too complex for this stage of the release cycle.  This patch fixes both
> the original problem that the earlier one did as well as 20050121-1.c.
>
> I have done a bootstrap using --with-cpu=power7 and make check, and there were
> no regressions other than the other --with-cpu=power7 that are not related to
> this patch:
>        gcc.dg/pr42461.c                (Peter Bergner has a fix)
>        gcc.dg/stack-usage-1.c          (patch submitted)
>        gcc.dg/sms-3.c                  (unknown)
>
> Is it ok to install the patch?
>
> 2011-02-01  Michael Meissner  <meissner@linux.vnet.ibm.com>
>
>        PR target/47580
>        * config/rs6000/vsx.md (vsx_float<VSi><mode>2): Use
>        gpc_reg_operand instead of vsx_register_operand to match rs6000.md
>        generator functions.
>        (vsx_floatuns<VSi><mode>2): Ditto.
>        (vsx_fix_trunc<mode><VSi>2): Ditto.
>        (vsx_fixuns_trunc<mode><VSi>2): Ditto.

Okay, but what is the long-term solution?  The more specific
predicates will be a patch for 4.7?

Thanks, David
Michael Meissner Feb. 3, 2011, 5:49 a.m. UTC | #2 
On Wed, Feb 02, 2011 at 04:29:52PM -0500, David Edelsohn wrote:
> Okay, but what is the long-term solution?  The more specific
> predicates will be a patch for 4.7?

As we discussed on the phone, the long term solution is to add new predicates
that more tightly match the registers (in particular, for the normal case, not
allowing GPRs or virtual registers, but it is complicated by the E500 having
floating point in GPRs for the expander).
diff mbox

Patch

Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md	(revision 169484)
+++ gcc/config/rs6000/vsx.md	(working copy)
@@ -708,33 +708,34 @@  (define_insn "vsx_copysign<mode>3"
 ;; the fprs because we don't want to add the altivec registers to movdi/movsi.
 ;; For the unsigned tests, there isn't a generic double -> unsigned conversion
 ;; in rs6000.md so don't test VECTOR_UNIT_VSX_P, just test against VSX.
+;; Don't use vsx_register_operand here, use gpc_reg_operand to match rs6000.md.
 (define_insn "vsx_float<VSi><mode>2"
-  [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-	(float:VSX_B (match_operand:<VSI> 1 "vsx_register_operand" "<VSr2>,<VSr3>")))]
+  [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa")
+	(float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))]
   "VECTOR_UNIT_VSX_P (<MODE>mode)"
   "x<VSv>cvsx<VSc><VSs> %x0,%x1"
   [(set_attr "type" "<VStype_simple>")
    (set_attr "fp_type" "<VSfptype_simple>")])
 
 (define_insn "vsx_floatuns<VSi><mode>2"
-  [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
-	(unsigned_float:VSX_B (match_operand:<VSI> 1 "vsx_register_operand" "<VSr2>,<VSr3>")))]
+  [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa")
+	(unsigned_float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))]
   "VECTOR_UNIT_VSX_P (<MODE>mode)"
   "x<VSv>cvux<VSc><VSs> %x0,%x1"
   [(set_attr "type" "<VStype_simple>")
    (set_attr "fp_type" "<VSfptype_simple>")])
 
 (define_insn "vsx_fix_trunc<mode><VSi>2"
-  [(set (match_operand:<VSI> 0 "vsx_register_operand" "=<VSr2>,?<VSr3>")
-	(fix:<VSI> (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]
+  [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
+	(fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))]
   "VECTOR_UNIT_VSX_P (<MODE>mode)"
   "x<VSv>cv<VSs>sx<VSc>s %x0,%x1"
   [(set_attr "type" "<VStype_simple>")
    (set_attr "fp_type" "<VSfptype_simple>")])
 
 (define_insn "vsx_fixuns_trunc<mode><VSi>2"
-  [(set (match_operand:<VSI> 0 "vsx_register_operand" "=<VSr2>,?<VSr3>")
-	(unsigned_fix:<VSI> (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]
+  [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
+	(unsigned_fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))]
   "VECTOR_UNIT_VSX_P (<MODE>mode)"
   "x<VSv>cv<VSs>ux<VSc>s %x0,%x1"
   [(set_attr "type" "<VStype_simple>")