From patchwork Tue Feb 1 19:08:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 81358 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id C4BC3B7109 for ; Wed, 2 Feb 2011 06:09:07 +1100 (EST) Received: (qmail 7861 invoked by alias); 1 Feb 2011 19:09:05 -0000 Received: (qmail 7853 invoked by uid 22791); 1 Feb 2011 19:09:05 -0000 X-SWARE-Spam-Status: No, hits=-1.6 required=5.0 tests=AWL, BAYES_00, NO_DNS_FOR_FROM, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from e7.ny.us.ibm.com (HELO e7.ny.us.ibm.com) (32.97.182.137) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 01 Feb 2011 19:09:00 +0000 Received: from d01dlp02.pok.ibm.com (d01dlp02.pok.ibm.com [9.56.224.85]) by e7.ny.us.ibm.com (8.14.4/8.13.1) with ESMTP id p11ImlWw012174 for ; Tue, 1 Feb 2011 13:49:21 -0500 Received: from d01relay06.pok.ibm.com (d01relay06.pok.ibm.com [9.56.227.116]) by d01dlp02.pok.ibm.com (Postfix) with ESMTP id 160594DE8026 for ; Tue, 1 Feb 2011 14:08:18 -0500 (EST) Received: from d01av01.pok.ibm.com (d01av01.pok.ibm.com [9.56.224.215]) by d01relay06.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p11J8lKX1986662 for ; Tue, 1 Feb 2011 14:08:48 -0500 Received: from d01av01.pok.ibm.com (loopback [127.0.0.1]) by d01av01.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p11J8lDF017109 for ; Tue, 1 Feb 2011 14:08:47 -0500 Received: from hungry-tiger.westford.ibm.com (sig-9-49-157-242.mts.ibm.com [9.49.157.242]) by d01av01.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id p11J8l6R017092; Tue, 1 Feb 2011 14:08:47 -0500 Received: by hungry-tiger.westford.ibm.com (Postfix, from userid 500) id 17DA9F8442; Tue, 1 Feb 2011 14:08:44 -0500 (EST) Date: Tue, 1 Feb 2011 14:08:44 -0500 From: Michael Meissner To: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com Subject: [PATCH] PR 47580: Fix corner case on powerpc using --with-cpu=power7 Message-ID: <20110201190844.GA15622@hungry-tiger.westford.ibm.com> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-Content-Scanned: Fidelis XPS MAILER X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org PR 47580 is a corner case that fails when the powerpc compiler is built with --with-cpu=power7 (or the test is run with -mcpu=power7). It fails due when you convert the address of the first stack variable to floating point, and the predicate in the VSX insn matching did not match the predicate in the expander. I have bootstrapped the compiler with --with-cpu=power7 (using the other patches that are under review) and ran make check tests. There were no regressions in the tests, and test gcc.dg/pr41551.c now passes. Is this ok to install? 2011-02-01 Michael Meissner PR target/47580 * config/rs6000/predicates.md (altivec_register_operand): Allow virtaul registers. (vsx_register_operand): Ditto. (vfloat_operand): Ditto. (vint_operand): Ditto. (vlogical_operand): Ditto. Index: gcc/config/rs6000/predicates.md =================================================================== --- gcc/config/rs6000/predicates.md (revision 169484) +++ gcc/config/rs6000/predicates.md (working copy) @@ -37,14 +37,14 @@ (define_predicate "altivec_register_oper (and (match_operand 0 "register_operand") (match_test "GET_CODE (op) != REG || ALTIVEC_REGNO_P (REGNO (op)) - || REGNO (op) > LAST_VIRTUAL_REGISTER"))) + || REGNO (op) > FIRST_VIRTUAL_REGISTER"))) ;; Return 1 if op is a VSX register. (define_predicate "vsx_register_operand" (and (match_operand 0 "register_operand") (match_test "GET_CODE (op) != REG || VSX_REGNO_P (REGNO (op)) - || REGNO (op) > LAST_VIRTUAL_REGISTER"))) + || REGNO (op) > FIRST_VIRTUAL_REGISTER"))) ;; Return 1 if op is a vector register that operates on floating point vectors ;; (either altivec or VSX). @@ -52,7 +52,7 @@ (define_predicate "vfloat_operand" (and (match_operand 0 "register_operand") (match_test "GET_CODE (op) != REG || VFLOAT_REGNO_P (REGNO (op)) - || REGNO (op) > LAST_VIRTUAL_REGISTER"))) + || REGNO (op) > FIRST_VIRTUAL_REGISTER"))) ;; Return 1 if op is a vector register that operates on integer vectors ;; (only altivec, VSX doesn't support integer vectors) @@ -60,7 +60,7 @@ (define_predicate "vint_operand" (and (match_operand 0 "register_operand") (match_test "GET_CODE (op) != REG || VINT_REGNO_P (REGNO (op)) - || REGNO (op) > LAST_VIRTUAL_REGISTER"))) + || REGNO (op) > FIRST_VIRTUAL_REGISTER"))) ;; Return 1 if op is a vector register to do logical operations on (and, or, ;; xor, etc.) @@ -68,7 +68,7 @@ (define_predicate "vlogical_operand" (and (match_operand 0 "register_operand") (match_test "GET_CODE (op) != REG || VLOGICAL_REGNO_P (REGNO (op)) - || REGNO (op) > LAST_VIRTUAL_REGISTER"))) + || REGNO (op) > FIRST_VIRTUAL_REGISTER"))) ;; Return 1 if op is the carry register. (define_predicate "ca_operand"