From patchwork Fri Oct 29 05:58:43 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: DJ Delorie X-Patchwork-Id: 69556 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 6F5B8B70A5 for ; Fri, 29 Oct 2010 16:58:56 +1100 (EST) Received: (qmail 1790 invoked by alias); 29 Oct 2010 05:58:53 -0000 Received: (qmail 1780 invoked by uid 22791); 29 Oct 2010 05:58:51 -0000 X-SWARE-Spam-Status: No, hits=-5.3 required=5.0 tests=AWL, BAYES_00, MAY_BE_FORGED, RCVD_IN_DNSWL_HI, SPF_HELO_PASS, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 29 Oct 2010 05:58:47 +0000 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id o9T5wjva022173 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Fri, 29 Oct 2010 01:58:46 -0400 Received: from greed.delorie.com ([10.3.112.3]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id o9T5wiUO026759 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 29 Oct 2010 01:58:45 -0400 Received: from greed.delorie.com (greed.delorie.com [127.0.0.1] (may be forged)) by greed.delorie.com (8.14.3/8.14.3) with ESMTP id o9T5whjS027916 for ; Fri, 29 Oct 2010 01:58:43 -0400 Received: (from dj@localhost) by greed.delorie.com (8.14.3/8.14.3/Submit) id o9T5whGR027913; Fri, 29 Oct 2010 01:58:43 -0400 Date: Fri, 29 Oct 2010 01:58:43 -0400 Message-Id: <201010290558.o9T5whGR027913@greed.delorie.com> From: DJ Delorie To: gcc-patches@gcc.gnu.org Subject: [rx] add register-specific constraints X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Some of the RX opcodes use specific registers, despite gcc's usual patterns not needing them. This adds constraints for those registers only so that source-level asm()s can refer to them. Ok? * config/rx/rx.h (R1_REGS, R2_REGS, R3_REGS, R4_REGS, R5_REGS, R45_REGS, R6_REGS): Add new register-specific classes. * config/rx/constraints: Add constaints for them. Index: constraints.md =================================================================== --- constraints.md (revision 166029) +++ constraints.md (working copy) @@ -83,6 +83,34 @@ (match_code "const_int" "01") ) ) ) ) ) + +(define_register_constraint "R01" + "R1_REGS" + "Register R1") + +(define_register_constraint "R02" + "R2_REGS" + "Register R2") + +(define_register_constraint "R03" + "R3_REGS" + "Register R3") + +(define_register_constraint "R04" + "R4_REGS" + "Register R4") + +(define_register_constraint "R05" + "R5_REGS" + "Register R5") + +(define_register_constraint "R45" + "R45_REGS" + "Register R5:R4") + +(define_register_constraint "R06" + "R6_REGS" + "Register R6") Index: rx.h =================================================================== --- rx.h (revision 166029) +++ rx.h (working copy) @@ -162,27 +162,48 @@ extern enum rx_cpu_types rx_cpu_type; #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND #define SHORT_IMMEDIATES_SIGN_EXTEND 1 enum reg_class { NO_REGS, /* No registers in set. */ + R1_REGS, + R2_REGS, + R3_REGS, + R4_REGS, + R5_REGS, + R45_REGS, + R6_REGS, GR_REGS, /* Integer registers. */ ALL_REGS, /* All registers. */ LIM_REG_CLASSES /* Max value + 1. */ }; #define REG_CLASS_NAMES \ { \ "NO_REGS", \ + "R1_REGS", \ + "R2_REGS", \ + "R3_REGS", \ + "R4_REGS", \ + "R5_REGS", \ + "R54_REGS", \ + "R6_REGS", \ "GR_REGS", \ "ALL_REGS" \ } #define REG_CLASS_CONTENTS \ { \ { 0x00000000 }, /* No registers, */ \ + { 0x00000002 }, \ + { 0x00000004 }, \ + { 0x00000008 }, \ + { 0x00000010 }, \ + { 0x00000020 }, \ + { 0x00000030 }, \ + { 0x00000040 }, \ { 0x0000ffff }, /* Integer registers. */ \ { 0x0000ffff } /* All registers. */ \ } #define IRA_COVER_CLASSES \ { \