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Pushed: [PATCH] MIPS: Fix wrong MSA FP vector negation

Message ID 1e966ed29e33be7f0c53513633abd6eba8185cdd.camel@xry111.site
State New
Headers show
Series Pushed: [PATCH] MIPS: Fix wrong MSA FP vector negation | expand

Commit Message

Xi Ruoyao Feb. 5, 2024, 12:25 p.m. UTC 
On Mon, 2024-02-05 at 09:56 +0800, YunQiang Su wrote:
> Xi Ruoyao <xry111@xry111.site> 于2024年2月5日周一 02:01写道：
> > 
> > We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is
> > wrong because -0.0 is not 0 - 0.0.  This causes some Python tests to
> > fail when Python is built with MSA enabled.
> > 
> > Use the bnegi.df instructions to simply reverse the sign bit instead.
> > 
> > gcc/ChangeLog:
> > 
> >          * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
> >          (neg<mode>2): Change the mode iterator from MSA to IMSA because
> >          in FP arithmetic we cannot use (0 - x) for -x.
> >          (neg<mode>2): New define_insn to implement FP vector negation,
> >          using a bnegi instruction to negate the sign bit.
> > ---
> > 
> > Bootstrapped and regtested on mips64el-linux-gnuabi64.  Ok for trunk
> > and/or release branches?
> > 
> >   gcc/config/mips/mips-msa.md | 18 +++++++++++++++---
> >   1 file changed, 15 insertions(+), 3 deletions(-)
> > 
> 
> LGTM, while I guess that we also need a test case.

Pushed to trunk and release branches, with a following obvious fix:


I'll write a test case for gcc.dg/vect later (now I have to do
$SOME_REAL_LIFE_THING...)
diff mbox series

Patch

diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md
index 920161ed1d8..779157f2a0c 100644
--- a/gcc/config/mips/mips-msa.md
+++ b/gcc/config/mips/mips-msa.md
@@ -613,7 +613,7 @@  (define_expand "neg<mode>2"
 
 (define_insn "neg<mode>2"
   [(set (match_operand:FMSA 0 "register_operand" "=f")
-       (neg (match_operand:FMSA 1 "register_operand" "f")))]
+       (neg:FMSA (match_operand:FMSA 1 "register_operand" "f")))]
   "ISA_HAS_MSA"
   "bnegi.<msafmt>\t%w0,%w1,<elmsgnbit>"
   [(set_attr "type" "simd_bit")