@@ -85,9 +85,6 @@ (define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]"
"VSX vector register to hold scalar double values or NO_REGS.")
-(define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]"
- "Altivec register to use for double loads/stores or NO_REGS.")
-
(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"
"FP or VSX register to perform float operations under -mvsx or NO_REGS.")
@@ -2515,7 +2515,6 @@ rs6000_debug_reg_global (void)
"wq reg_class = %s\n"
"wr reg_class = %s\n"
"ws reg_class = %s\n"
- "wv reg_class = %s\n"
"ww reg_class = %s\n"
"wx reg_class = %s\n"
"wA reg_class = %s\n"
@@ -2531,7 +2530,6 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
@@ -3147,7 +3145,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
wn - always NO_REGS.
wr - GPR if 64-bit mode is permitted.
ws - Register class to do ISA 2.06 DF operations.
- wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
ww - Register class to do SF conversions in with VSX operations.
wx - Float register if we can do 32-bit int stores. */
@@ -3163,7 +3160,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
- rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
}
/* Add conditional constraints based on various options, to allow us to
@@ -1263,7 +1263,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
RS6000_CONSTRAINT_ws, /* VSX register for DF */
- RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */
RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
@@ -475,7 +475,7 @@ (define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
(define_mode_attr f64_dm [(DF "ws") (DD "d")])
; Definitions for 64-bit use of altivec registers
-(define_mode_attr f64_av [(DF "wv") (DD "wn")])
+(define_mode_attr f64_av [(DF "v") (DD "wn")])
; Definitions for 64-bit access to ISA 3.0 (power9) vector
(define_mode_attr f64_p9 [(DF "v") (DD "wn")])
@@ -7611,7 +7611,7 @@ (define_insn "*mov<mode>_hardfloat32"
8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
- *, *, *, *, *,
+ p7v, p7v, *, *, *,
*, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -7682,7 +7682,7 @@ (define_insn "*mov<mode>_hardfloat64"
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
- *, *, *, *, *,
+ p7v, p7v, *, *, *,
*, *, *, *, *,
*, p8v, p8v")])
@@ -8742,12 +8742,12 @@ (define_insn_and_split "reload_gpr_from_vsxsf"
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- r, wY, Z, ^v, $wv, ^wa,
- wa, wa, wv, wa, *i, wv,
- wv")
+ r, wY, Z, ^v, $v, ^wa,
+ wa, wa, v, wa, *i, v,
+ v")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- IJKnF, ^v, $wv, wY, Z, ^wa,
+ IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
"! TARGET_POWERPC64
@@ -8786,9 +8786,9 @@ (define_insn "*movdi_internal32"
4")
(set_attr "isa"
"*, *, *, *, *, *,
- *, p9v, *, p9v, *, *,
- p9v, p9v, *, *, *, *,
- *")])
+ *, p9v, p7v, p9v, p7v, *,
+ p9v, p9v, p7v, *, *, p7v,
+ p7v")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand")
@@ -8826,12 +8826,12 @@ (define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r, r, r, r,
m, ^d, ^d, wY, Z, $v,
- $wv, ^wa, wa, wa, wv, wa,
- wa, wv, wv, r, *h, *h,
+ $v, ^wa, wa, wa, v, wa,
+ wa, v, v, r, *h, *h,
?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r, I, L, nF,
- ^d, m, ^d, ^v, $wv, wY,
+ ^d, m, ^d, ^v, $v, wY,
Z, ^wa, Oj, wM, OjwM, Oj,
wM, wS, wB, *h, r, 0,
wa, r"))]
@@ -8880,9 +8880,9 @@ (define_insn "*movdi_internal64"
4, 4")
(set_attr "isa"
"*, *, *, *, *, *,
- *, *, *, p9v, *, p9v,
- *, *, p9v, p9v, *, *,
- *, *, *, *, *, *,
+ *, *, *, p9v, p7v, p9v,
+ p7v, *, p9v, p9v, p7v, *,
+ *, p7v, p7v, *, *, *,
p8v, p8v")])
; Some DImode loads are best done as a load of -1 followed by a mask
@@ -3273,7 +3273,7 @@ (define_insn_and_split "*vsx_extract_<P:mode>_<VSX_D:mode>_load"
(define_insn "*vsx_extract_<mode>_store"
[(set (match_operand:<VS_scalar> 0 "memory_operand" "=m,Z,wY")
(vec_select:<VS_scalar>
- (match_operand:VSX_D 1 "register_operand" "d,wv,v")
+ (match_operand:VSX_D 1 "register_operand" "d,v,v")
(parallel [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"@
@@ -3281,7 +3281,7 @@ (define_insn "*vsx_extract_<mode>_store"
stxsdx %x1,%y0
stxsd %1,%0"
[(set_attr "type" "fpstore")
- (set_attr "isa" "*,*,p9v")])
+ (set_attr "isa" "*,p7v,p9v")])
;; Variable V2DI/V2DF extract shift
(define_insn "vsx_vslo_<mode>"
@@ -3346,7 +3346,7 @@ (define_insn_and_split "vsx_extract_v4sf"
(set_attr "type" "fp")])
(define_insn_and_split "*vsx_extract_v4sf_<mode>_load"
- [(set (match_operand:SF 0 "register_operand" "=f,wv,v,?r")
+ [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
(match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
(parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
@@ -3361,7 +3361,7 @@ (define_insn_and_split "*vsx_extract_v4sf_<mode>_load"
}
[(set_attr "type" "fpload,fpload,fpload,load")
(set_attr "length" "8")
- (set_attr "isa" "*,*,p9v,*")])
+ (set_attr "isa" "*,p7v,p9v,*")])
;; Variable V4SF extract
(define_insn_and_split "vsx_extract_v4sf_var"
@@ -3197,7 +3197,7 @@ Altivec vector register
Any VSX register if the @option{-mvsx} option was used or NO_REGS.
When using any of the register constraints (@code{wa}, @code{wd}, @code{wf},
-@code{wp}, @code{wq}, @code{ws}, @code{wv}, or @code{ww})
+@code{wp}, @code{wq}, @code{ws}, or @code{ww})
that take VSX registers, you must use @code{%x<n>} in the template so
that the correct register is used. Otherwise the register number
output in the assembly file will be incorrect if an Altivec register
@@ -3269,9 +3269,6 @@ General purpose register if 64-bit instructions are enabled or NO_REGS.
@item ws
VSX vector register to hold scalar double values or NO_REGS.
-@item wv
-Altivec register to use for double loads/stores or NO_REGS.
-
@item ww
FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.