From patchwork Sat Nov 28 12:04:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Botcazou X-Patchwork-Id: 1407518 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=adacore.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=adacore-com.20150623.gappssmtp.com header.i=@adacore-com.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=N9IbP8Ip; dkim-atps=neutral Received: from sourceware.org (unknown [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Cjqt02yk4z9s1l for ; Sat, 28 Nov 2020 23:04:21 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6E8503858024; Sat, 28 Nov 2020 12:04:19 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by sourceware.org (Postfix) with ESMTPS id 413C73858024 for ; Sat, 28 Nov 2020 12:04:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 413C73858024 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=adacore.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=botcazou@adacore.com Received: by mail-wr1-x436.google.com with SMTP id 64so8319524wra.11 for ; Sat, 28 Nov 2020 04:04:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=adacore-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=R1SfwW/ifHmCoYSJj81Tr/ajxIPXhD7cURjpcgi/FMc=; b=N9IbP8Ip1X5hTpUgPEqKxnhSjkjzjFqQy5THKzsCSpFtCHB1tytMahakRGJOs3r0h/ /1qUwqMo61pcKAj4MTsii6qHYNoMurpBrCa7NEZ2KrDqy6/jK1RNeN5YgrQ+indsb2WP v7aowxmNSN7b9f60fpOVokisbgSd48rwi2UQLlscjyCOZfYJte5qq66FgXuo1neRRQ3F Ht1ZUAIf0N90dn/Xmkk8RhAb7bYBi3wp1cl3ZH9DoQxwphlSI9M7AfzI8iQYY3kJkSf9 xK9HKWtoN+3aJq+VS0P446NeX9fTLaQqZiWpK2zWjYG306vlIsmzx6ICeZrZnm53/XGx ZgtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=R1SfwW/ifHmCoYSJj81Tr/ajxIPXhD7cURjpcgi/FMc=; b=ujyKZlPHfyAgzONyML0L1JPa+GN2b53QxshLdfZIoyRWQ4/RDd2Eret1V4GNwzpMn1 PrC4hts7HIGWBh1nJGYBQQQ1ASQrZf7Xu20C3zQGU7sn18RQpveuwhihfwESYH4DvD+E f0zlVFEhMW/aqHcDgjtTMKzwt7aMRw6oUIIXhjYg6yN0AQit7GLA9sFKX6Tsi/9ftUN0 KPNJHhl4w8G//x/+3hcGHrLQBHl6CSltkWyHq04FoQKm7Wyn0WbJ6k/8ga2BlIMvlHvW hgED7UZxklJSy6v+aAwIulcdTA9wF5R6nrinNExMT1HK0kBv5R6TxYvCSieI6ZOG6tuD 3Kug== X-Gm-Message-State: AOAM532v1k9mPgZPOztQXs5P/sCUz6vMk3PkUzMHy8Pq0NqGi9UNEH4b 78Qq5Cj8dJarQcKNe6IarSETPZ1aciMp4Mx4 X-Google-Smtp-Source: ABdhPJzodlBvv4MpPOsf0V5jvgh0wy3JyhEgn7vKug8el+pxSf7/43ihtMA9QrqEPa2Q9PvvKpUZWw== X-Received: by 2002:adf:e447:: with SMTP id t7mr17430377wrm.218.1606565054022; Sat, 28 Nov 2020 04:04:14 -0800 (PST) Received: from fomalhaut.localnet ([2a01:e0a:41b:9230:7f82:53f4:769e:54b6]) by smtp.gmail.com with ESMTPSA id o5sm17250287wmh.8.2020.11.28.04.04.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 28 Nov 2020 04:04:13 -0800 (PST) From: Eric Botcazou X-Google-Original-From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [SPARC] Fix PR target/97939 Date: Sat, 28 Nov 2020 13:04:11 +0100 Message-ID: <1820484.lRnZXo2R17@fomalhaut> MIME-Version: 1.0 X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" I overlooked the little dance around 4096 that the add/sub instructions do on the SPARC when implementing the overflow arithmetic operations. It cannot be done for unsigned overflow, but it can be done for signed overflow. Tested on SPARC64/Linux and SPARC/Solaris, applied on the mainline, 10 and 9 branches. 2020-11-28 Eric Botcazou PR target/97939 * config/sparc/predicates.md (arith_double_add_operand): Comment. * config/sparc/sparc.md (uaddvdi4): Use arith_double_operand. (addvdi4): Use arith_double_add_operand. (addsi3): Remove useless attributes. (addvsi4): Use arith_add_operand. (*cmp_ccv_plus): Likewise and add second alternative accordingly. (*cmp_ccxv_plus): Likewise. (*cmp_ccv_plus_set): Likewise. (*cmp_ccxv_plus_set): Likewise. (*cmp_ccv_plus_sltu_set): Likewise. (usubvdi4): Use arith_double_operand. (subvdi4): Use arith_double_add_operand. (subsi3): Remove useless attributes. (subvsi4): Use arith_add_operand. (*cmp_ccv_minus): Likewise and add second alternative accordingly. (*cmp_ccxv_minus): Likewise. (*cmp_ccv_minus_set): Likewise. (*cmp_ccxv_minus_set): Likewise. (*cmp_ccv_minus_sltu_set): Likewise. (negsi2): Use register_operand. (unegvsi3): Likewise. (negvsi3) Likewise. (*cmp_ccnz_neg): Likewise. (*cmp_ccxnz_neg): Likewise. (*cmp_ccnz_neg_set): Likewise. (*cmp_ccxnz_neg_set): Likewise. (*cmp_ccc_neg_set): Likewise. (*cmp_ccxc_neg_set): Likewise. (*cmp_ccc_neg_sltu_set): Likewise. (*cmp_ccv_neg): Likewise. (*cmp_ccxv_neg): Likewise. (*cmp_ccv_neg_set): Likewise. (*cmp_ccxv_neg_set): Likewise. (*cmp_ccv_neg_sltu_set): Likewise. 2020-11-28 Eric Botcazou * gcc.target/sparc/overflow-6.c: New test. diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md index 3d4997211ca..42316adc94e 100644 --- a/gcc/config/sparc/predicates.md +++ b/gcc/config/sparc/predicates.md @@ -296,6 +296,8 @@ if (arith_double_operand (op, mode)) return true; + /* Turning an add/sub instruction into the other changes the Carry flag + so the 4096 trick cannot be used for double operations in 32-bit mode. */ return TARGET_ARCH64 && const_4096_operand (op, mode); }) diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index edfb6353683..6e9ccb4ecfd 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -3768,10 +3768,13 @@ visl") } }) +;; Turning an add/sub instruction into the other changes the Carry flag +;; so the 4096 trick cannot be used for operations in CCXCmode. + (define_expand "uaddvdi4" [(parallel [(set (reg:CCXC CC_REG) (compare:CCXC (plus:DI (match_operand:DI 1 "register_operand") - (match_operand:DI 2 "arith_add_operand")) + (match_operand:DI 2 "arith_double_operand")) (match_dup 1))) (set (match_operand:DI 0 "register_operand") (plus:DI (match_dup 1) (match_dup 2)))]) @@ -3790,10 +3793,13 @@ visl") } }) +;; Turning an add/sub instruction into the other does not change the Overflow +;; flag so the 4096 trick can be used for operations in CCXVmode. + (define_expand "addvdi4" [(parallel [(set (reg:CCXV CC_REG) (compare:CCXV (plus:DI (match_operand:DI 1 "register_operand") - (match_operand:DI 2 "arith_add_operand")) + (match_operand:DI 2 "arith_double_add_operand")) (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV))) (set (match_operand:DI 0 "register_operand") @@ -3966,9 +3972,10 @@ visl") "" "@ add\t%1, %2, %0 - sub\t%1, -%2, %0" - [(set_attr "type" "*,*") - (set_attr "fptype" "*,*")]) + sub\t%1, -%2, %0") + +;; Turning an add/sub instruction into the other changes the Carry flag +;; so the 4096 trick cannot be used for operations in CCCmode. (define_expand "uaddvsi4" [(parallel [(set (reg:CCC CC_REG) @@ -3982,10 +3989,13 @@ visl") (pc)))] "") +;; Turning an add/sub instruction into the other does not change the Overflow +;; flag so the 4096 trick can be used for operations in CCVmode. + (define_expand "addvsi4" [(parallel [(set (reg:CCV CC_REG) (compare:CCV (plus:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "arith_operand")) + (match_operand:SI 2 "arith_add_operand")) (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV))) (set (match_operand:SI 0 "register_operand") @@ -4094,42 +4104,50 @@ visl") (define_insn "*cmp_ccv_plus" [(set (reg:CCV CC_REG) - (compare:CCV (plus:SI (match_operand:SI 0 "register_operand" "%r") - (match_operand:SI 1 "arith_operand" "rI")) + (compare:CCV (plus:SI (match_operand:SI 0 "register_operand" "%r,r") + (match_operand:SI 1 "arith_add_operand" "rI,O")) (unspec:SI [(match_dup 0) (match_dup 1)] UNSPEC_ADDV)))] "" - "addcc\t%0, %1, %%g0" + "@ + addcc\t%0, %1, %%g0 + subcc\t%0, -%1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccxv_plus" [(set (reg:CCXV CC_REG) - (compare:CCXV (plus:DI (match_operand:DI 0 "register_operand" "%r") - (match_operand:DI 1 "arith_operand" "rI")) + (compare:CCXV (plus:DI (match_operand:DI 0 "register_operand" "%r,r") + (match_operand:DI 1 "arith_add_operand" "rI,O")) (unspec:DI [(match_dup 0) (match_dup 1)] UNSPEC_ADDV)))] "TARGET_ARCH64" - "addcc\t%0, %1, %%g0" + "@ + addcc\t%0, %1, %%g0 + subcc\t%0, -%1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccv_plus_set" [(set (reg:CCV CC_REG) - (compare:CCV (plus:SI (match_operand:SI 1 "register_operand" "%r") - (match_operand:SI 2 "arith_operand" "rI")) + (compare:CCV (plus:SI (match_operand:SI 1 "register_operand" "%r,r") + (match_operand:SI 2 "arith_add_operand" "rI,O")) (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV))) - (set (match_operand:SI 0 "register_operand" "=r") + (set (match_operand:SI 0 "register_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] "" - "addcc\t%1, %2, %0" + "@ + addcc\t%1, %2, %0 + subcc\t%1, -%2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccxv_plus_set" [(set (reg:CCXV CC_REG) - (compare:CCXV (plus:DI (match_operand:DI 1 "register_operand" "%r") - (match_operand:DI 2 "arith_operand" "rI")) + (compare:CCXV (plus:DI (match_operand:DI 1 "register_operand" "%r,r") + (match_operand:DI 2 "arith_add_operand" "rI,O")) (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV))) - (set (match_operand:DI 0 "register_operand" "=r") + (set (match_operand:DI 0 "register_operand" "=r,r") (plus:DI (match_dup 1) (match_dup 2)))] "TARGET_ARCH64" - "addcc\t%1, %2, %0" + "@ + addcc\t%1, %2, %0 + subcc\t%1, -%2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccv_plus_sltu_set" @@ -4161,10 +4179,13 @@ visl") } }) +;; Turning an add/sub instruction into the other changes the Carry flag +;; so the 4096 trick cannot be used for operations in CCXmode. + (define_expand "usubvdi4" [(parallel [(set (reg:CCX CC_REG) (compare:CCX (match_operand:DI 1 "register_or_zero_operand") - (match_operand:DI 2 "arith_add_operand"))) + (match_operand:DI 2 "arith_double_operand"))) (set (match_operand:DI 0 "register_operand") (minus:DI (match_dup 1) (match_dup 2)))]) (set (pc) (if_then_else (ltu (reg:CCX CC_REG) (const_int 0)) @@ -4188,10 +4209,13 @@ visl") } }) +;; Turning an add/sub instruction into the other does not change the Overflow +;; flag so the 4096 trick can be used for operations in CCXVmode. + (define_expand "subvdi4" [(parallel [(set (reg:CCXV CC_REG) (compare:CCXV (minus:DI (match_operand:DI 1 "register_operand") - (match_operand:DI 2 "arith_add_operand")) + (match_operand:DI 2 "arith_double_add_operand")) (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV))) (set (match_operand:DI 0 "register_operand") @@ -4362,9 +4386,10 @@ visl") "" "@ sub\t%1, %2, %0 - add\t%1, -%2, %0" - [(set_attr "type" "*,*") - (set_attr "fptype" "*,*")]) + add\t%1, -%2, %0") + +;; Turning an add/sub instruction into the other changes the Carry flag +;; so the 4096 trick cannot be used for operations in CCmode. (define_expand "usubvsi4" [(parallel [(set (reg:CC CC_REG) @@ -4384,10 +4409,13 @@ visl") } }) +;; Turning an add/sub instruction into the other does not change the Overflow +;; flag so the 4096 trick can be used for operations in CCVmode. + (define_expand "subvsi4" [(parallel [(set (reg:CCV CC_REG) (compare:CCV (minus:SI (match_operand:SI 1 "register_operand") - (match_operand:SI 2 "arith_operand")) + (match_operand:SI 2 "arith_add_operand")) (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV))) (set (match_operand:SI 0 "register_operand") @@ -4480,42 +4508,50 @@ visl") (define_insn "*cmp_ccv_minus" [(set (reg:CCV CC_REG) - (compare:CCV (minus:SI (match_operand:SI 0 "register_or_zero_operand" "rJ") - (match_operand:SI 1 "arith_operand" "rI")) + (compare:CCV (minus:SI (match_operand:SI 0 "register_or_zero_operand" "rJ,rJ") + (match_operand:SI 1 "arith_add_operand" "rI,O")) (unspec:SI [(match_dup 0) (match_dup 1)] UNSPEC_SUBV)))] "" - "subcc\t%r0, %1, %%g0" + "@ + subcc\t%r0, %1, %%g0 + addcc\t%r0, -%1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccxv_minus" [(set (reg:CCXV CC_REG) - (compare:CCXV (minus:DI (match_operand:DI 0 "register_or_zero_operand" "rJ") - (match_operand:DI 1 "arith_operand" "rI")) + (compare:CCXV (minus:DI (match_operand:DI 0 "register_or_zero_operand" "rJ,rJ") + (match_operand:DI 1 "arith_add_operand" "rI,O")) (unspec:DI [(match_dup 0) (match_dup 1)] UNSPEC_SUBV)))] "TARGET_ARCH64" - "subcc\t%r0, %1, %%g0" + "@ + subcc\t%r0, %1, %%g0 + addcc\t%r0, -%1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccv_minus_set" [(set (reg:CCV CC_REG) - (compare:CCV (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ") - (match_operand:SI 2 "arith_operand" "rI")) + (compare:CCV (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ") + (match_operand:SI 2 "arith_add_operand" "rI,O")) (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV))) - (set (match_operand:SI 0 "register_operand" "=r") + (set (match_operand:SI 0 "register_operand" "=r,r") (minus:SI (match_dup 1) (match_dup 2)))] "" - "subcc\t%r1, %2, %0" + "@ + subcc\t%r1, %2, %0 + addcc\t%r1, -%2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccxv_minus_set" [(set (reg:CCXV CC_REG) - (compare:CCXV (minus:DI (match_operand:DI 1 "register_or_zero_operand" "rJ") - (match_operand:DI 2 "arith_operand" "rI")) + (compare:CCXV (minus:DI (match_operand:DI 1 "register_or_zero_operand" "rJ,rJ") + (match_operand:DI 2 "arith_add_operand" "rI,O")) (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV))) - (set (match_operand:DI 0 "register_operand" "=r") + (set (match_operand:DI 0 "register_operand" "=r,r") (minus:DI (match_dup 1) (match_dup 2)))] "TARGET_ARCH64" - "subcc\t%r1, %2, %0" + "@ + subcc\t%r1, %2, %0 + addcc\t%r1, -%2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccv_minus_sltu_set" @@ -5766,13 +5802,13 @@ visl") (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=r") - (neg:SI (match_operand:SI 1 "arith_operand" "rI")))] + (neg:SI (match_operand:SI 1 "register_operand" "r")))] "" "sub\t%%g0, %1, %0") (define_expand "unegvsi3" [(parallel [(set (reg:CCC CC_REG) - (compare:CCC (not:SI (match_operand:SI 1 "arith_operand" "")) + (compare:CCC (not:SI (match_operand:SI 1 "register_operand" "")) (const_int -1))) (set (match_operand:SI 0 "register_operand" "") (neg:SI (match_dup 1)))]) @@ -5784,7 +5820,7 @@ visl") (define_expand "negvsi3" [(parallel [(set (reg:CCV CC_REG) - (compare:CCV (neg:SI (match_operand:SI 1 "arith_operand" "")) + (compare:CCV (neg:SI (match_operand:SI 1 "register_operand" "")) (unspec:SI [(match_dup 1)] UNSPEC_NEGV))) (set (match_operand:SI 0 "register_operand" "") (neg:SI (match_dup 1)))]) @@ -5796,7 +5832,7 @@ visl") (define_insn "*cmp_ccnz_neg" [(set (reg:CCNZ CC_REG) - (compare:CCNZ (neg:SI (match_operand:SI 0 "arith_operand" "rI")) + (compare:CCNZ (neg:SI (match_operand:SI 0 "register_operand" "r")) (const_int 0)))] "" "subcc\t%%g0, %0, %%g0" @@ -5804,7 +5840,7 @@ visl") (define_insn "*cmp_ccxnz_neg" [(set (reg:CCXNZ CC_REG) - (compare:CCXNZ (neg:DI (match_operand:DI 0 "arith_operand" "rI")) + (compare:CCXNZ (neg:DI (match_operand:DI 0 "register_operand" "r")) (const_int 0)))] "TARGET_ARCH64" "subcc\t%%g0, %0, %%g0" @@ -5812,7 +5848,7 @@ visl") (define_insn "*cmp_ccnz_neg_set" [(set (reg:CCNZ CC_REG) - (compare:CCNZ (neg:SI (match_operand:SI 1 "arith_operand" "rI")) + (compare:CCNZ (neg:SI (match_operand:SI 1 "register_operand" "r")) (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_dup 1)))] @@ -5822,7 +5858,7 @@ visl") (define_insn "*cmp_ccxnz_neg_set" [(set (reg:CCXNZ CC_REG) - (compare:CCXNZ (neg:DI (match_operand:DI 1 "arith_operand" "rI")) + (compare:CCXNZ (neg:DI (match_operand:DI 1 "register_operand" "r")) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_dup 1)))] @@ -5832,7 +5868,7 @@ visl") (define_insn "*cmp_ccc_neg_set" [(set (reg:CCC CC_REG) - (compare:CCC (not:SI (match_operand:SI 1 "arith_operand" "rI")) + (compare:CCC (not:SI (match_operand:SI 1 "register_operand" "r")) (const_int -1))) (set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_dup 1)))] @@ -5842,7 +5878,7 @@ visl") (define_insn "*cmp_ccxc_neg_set" [(set (reg:CCXC CC_REG) - (compare:CCXC (not:DI (match_operand:DI 1 "arith_operand" "rI")) + (compare:CCXC (not:DI (match_operand:DI 1 "register_operand" "r")) (const_int -1))) (set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_dup 1)))] @@ -5853,7 +5889,7 @@ visl") (define_insn "*cmp_ccc_neg_sltu_set" [(set (reg:CCC CC_REG) (compare:CCC (zero_extend:DI - (neg:SI (plus:SI (match_operand:SI 1 "arith_operand" "rI") + (neg:SI (plus:SI (match_operand:SI 1 "register_operand" "r") (ltu:SI (reg:CCC CC_REG) (const_int 0))))) (neg:DI (plus:DI (zero_extend:DI (match_dup 1)) @@ -5868,7 +5904,7 @@ visl") (define_insn "*cmp_ccv_neg" [(set (reg:CCV CC_REG) - (compare:CCV (neg:SI (match_operand:SI 0 "arith_operand" "rI")) + (compare:CCV (neg:SI (match_operand:SI 0 "register_operand" "r")) (unspec:SI [(match_dup 0)] UNSPEC_NEGV)))] "" "subcc\t%%g0, %0, %%g0" @@ -5876,7 +5912,7 @@ visl") (define_insn "*cmp_ccxv_neg" [(set (reg:CCXV CC_REG) - (compare:CCXV (neg:DI (match_operand:DI 0 "arith_operand" "rI")) + (compare:CCXV (neg:DI (match_operand:DI 0 "register_operand" "r")) (unspec:DI [(match_dup 0)] UNSPEC_NEGV)))] "TARGET_ARCH64" "subcc\t%%g0, %0, %%g0" @@ -5884,7 +5920,7 @@ visl") (define_insn "*cmp_ccv_neg_set" [(set (reg:CCV CC_REG) - (compare:CCV (neg:SI (match_operand:SI 1 "arith_operand" "rI")) + (compare:CCV (neg:SI (match_operand:SI 1 "register_operand" "r")) (unspec:SI [(match_dup 1)] UNSPEC_NEGV))) (set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_dup 1)))] @@ -5894,7 +5930,7 @@ visl") (define_insn "*cmp_ccxv_neg_set" [(set (reg:CCXV CC_REG) - (compare:CCXV (neg:DI (match_operand:DI 1 "arith_operand" "rI")) + (compare:CCXV (neg:DI (match_operand:DI 1 "register_operand" "r")) (unspec:DI [(match_dup 1)] UNSPEC_NEGV))) (set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_dup 1)))] @@ -5904,7 +5940,7 @@ visl") (define_insn "*cmp_ccv_neg_sltu_set" [(set (reg:CCV CC_REG) - (compare:CCV (neg:SI (plus:SI (match_operand:SI 1 "arith_operand" "rI") + (compare:CCV (neg:SI (plus:SI (match_operand:SI 1 "register_operand" "r") (ltu:SI (reg:CCC CC_REG) (const_int 0)))) (unspec:SI [(plus:SI (match_dup 1) (ltu:SI (reg:CCC CC_REG)