diff mbox

[AArch64] Restrict the shift value in compare extended shift operation

Message ID 17c1ef6462fc49f58001d169ffe029ed@SN2PR07MB029.namprd07.prod.outlook.com
State New
Headers show

Commit Message

Hurugalawadi, Naveen May 7, 2013, 10:35 a.m. UTC 
Hi,

Please find attached the patch that restricts the shift value in
comparison operation between 0-4.

Please review the patch and let me know if its okay?

2013-05-07  Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64.md
	(cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>): Restrict the
	shift value between 0-4.

Thanks,
Naveen

Comments

Marcus Shawcroft May 7, 2013, 10:56 a.m. UTC | #1 
OK

On 7 May 2013 11:35, Hurugalawadi, Naveen
<Naveen.Hurugalawadi@caviumnetworks.com> wrote:
> Hi,
>
> Please find attached the patch that restricts the shift value in
> comparison operation between 0-4.
>
> Please review the patch and let me know if its okay?
>
> 2013-05-07  Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
>
>         * config/aarch64/aarch64.md
>         (cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>): Restrict the
>         shift value between 0-4.
>
> Thanks,
> Naveen
diff mbox

Patch

--- gcc/config/aarch64/aarch64.md	2013-05-07 11:31:52.096213714 +0530
+++ gcc/config/aarch64/aarch64.md	2013-05-07 12:53:04.016369788 +0530
@@ -2349,7 +2349,7 @@ 
 	(compare:CC_SWP (ashift:GPI
 			 (ANY_EXTEND:GPI
 			  (match_operand:ALLX 0 "register_operand" "r"))
-			 (match_operand:QI 1 "aarch64_shift_imm_<mode>" "n"))
+			 (match_operand 1 "aarch64_imm3" "Ui3"))
 	(match_operand:GPI 2 "register_operand" "r")))]
   ""
   "cmp\\t%<GPI:w>2, %<GPI:w>0, <su>xt<ALLX:size> %1"