From patchwork Thu Feb 10 00:48:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 1590754 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=w6fFy/Ml; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JvJ6g4WsNz9s8s for ; Thu, 10 Feb 2022 11:49:30 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EF8EC3858D1E for ; Thu, 10 Feb 2022 00:49:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EF8EC3858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1644454167; bh=AxMy0B0CloBqoLA+sM+oPto+5auUt64Hzr193fRK7hc=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=w6fFy/MlgMub7tZLjbSy4mr87/fvOqFrVL1lTZY2mW1FB6gLFnB9w1wIe/5TtUnrr nHrFwsZxiKCppwCm3FOg5nw802i1iIyiK3V/HZ5mouh3iy5IOrdCNDGVziXKDFNdyy MJwwbmUpMXXkn8hIRsq0SD+cNND63HqrerE3Powk= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 8F7763858D1E for ; Thu, 10 Feb 2022 00:48:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8F7763858D1E Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21A0V0us025534 for ; Wed, 9 Feb 2022 16:48:44 -0800 Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3e4r8001ta-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 09 Feb 2022 16:48:44 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 9 Feb 2022 16:48:42 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 9 Feb 2022 16:48:42 -0800 Received: from linux.wrightpinski.org.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id 7E1F23F7055; Wed, 9 Feb 2022 16:48:42 -0800 (PST) To: Subject: [PATCH] [COMMITTED] Fix PR aarch64/104474: ICE with vector float initializers and non-consts. Date: Wed, 9 Feb 2022 16:48:36 -0800 Message-ID: <1644454116-23332-1-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 X-Proofpoint-GUID: YtbsqZh7mJi0eKYRJir8tW1shkRx_z1N X-Proofpoint-ORIG-GUID: YtbsqZh7mJi0eKYRJir8tW1shkRx_z1N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-09_12,2022-02-09_01,2021-12-02_01 X-Spam-Status: No, score=-14.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: apinski--- via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: apinski@marvell.com Cc: Andrew Pinski Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Andrew Pinski The problem here is that the aarch64 back-end was placing const0_rtx into the constant vector RTL even if the mode was a floating point mode. The fix is instead to use CONST0_RTX and pass the mode to select the correct zero (either const_int or const_double). Committed as obvious after a bootstrap/test on aarch64-linux-gnu with no regressions. PR target/104474 gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_sve_expand_vector_init_handle_trailing_constants): Use CONST0_RTX instead of const0_rtx for the non-constant elements. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/pr104474-1.c: New test. * gcc.target/aarch64/sve/pr104474-2.c: New test. * gcc.target/aarch64/sve/pr104474-3.c: New test. --- gcc/config/aarch64/aarch64.cc | 2 +- gcc/testsuite/gcc.target/aarch64/sve/pr104474-1.c | 9 +++++++++ gcc/testsuite/gcc.target/aarch64/sve/pr104474-2.c | 9 +++++++++ gcc/testsuite/gcc.target/aarch64/sve/pr104474-3.c | 9 +++++++++ 4 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr104474-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr104474-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr104474-3.c diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 8dc6d55e0f2..828ee472be2 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -21164,7 +21164,7 @@ aarch64_sve_expand_vector_init_handle_trailing_constants { rtx x = builder.elt (i + nelts_reqd - n_trailing_constants); if (!valid_for_const_vector_p (elem_mode, x)) - x = const0_rtx; + x = CONST0_RTX (elem_mode); v.quick_push (x); } rtx const_vec = v.build (); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr104474-1.c b/gcc/testsuite/gcc.target/aarch64/sve/pr104474-1.c new file mode 100644 index 00000000000..9e5bfe64467 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr104474-1.c @@ -0,0 +1,9 @@ +/* { dg-options "-mcpu=neoverse-512tvb -frounding-math -msve-vector-bits=512" } */ + +typedef float __attribute__((__vector_size__ (64))) F; + +F +foo (void) +{ + return (F){68435453, 0, 0, 0, 0, 0, 0, 5, 0, 431144844}; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr104474-2.c b/gcc/testsuite/gcc.target/aarch64/sve/pr104474-2.c new file mode 100644 index 00000000000..02a4b6a8fdc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr104474-2.c @@ -0,0 +1,9 @@ +/* { dg-options "-mcpu=neoverse-512tvb -msve-vector-bits=512" } */ + +typedef float __attribute__((__vector_size__ (64))) F; + +F +foo (float t) +{ + return (F){t, 0, 0, 0, 0, 0, 0, 5, 0, t}; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr104474-3.c b/gcc/testsuite/gcc.target/aarch64/sve/pr104474-3.c new file mode 100644 index 00000000000..7bed0142968 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr104474-3.c @@ -0,0 +1,9 @@ +/* { dg-options "-mcpu=neoverse-v1 -frounding-math -msve-vector-bits=256" } */ + +typedef _Float16 __attribute__((__vector_size__ (32))) F; + +F +foo (void) +{ + return (F){0, 6270, 0, 0, 0, 0, 0, 0, 3229, 0, 40}; +}