[12/14] S/390: arch13: vector shift double by bit builtins

Message ID	1554204061-30488-13-git-send-email-krebbel@linux.ibm.com
State	New
Headers	show Return-Path: <gcc-patches-return-498749-incoming=patchwork.ozlabs.org@gcc.gnu.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:in-reply-to:references:message-id; q=dns; s= default; b=pCu+YUQFtojlSkrbLNabdCEvGMFfOx5h+bzXEfGJm8D1jQ56geYAi yVurTdqq3p0oQ8fae5UTzZN7EsA0Ml1BhTNK8+0v34y27dpAyYJCN1wtxZQ0K+Rc DAeKA054vErkX6aDTF4M+G84TApvPq5wjauzwEj5PhWNSWdDea1Ii8= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org Gateway: Authorized Use Only! Violators will be prosecuted for <gcc-patches@gcc.gnu.org> from <krebbel@linux.ibm.com>; Tue, 2 Apr 2019 12:21:21 +0100 Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 2 Apr 2019 12:21:19 +0100 From: Andreas Krebbel <krebbel@linux.ibm.com> To: gcc-patches@gcc.gnu.org Subject: [PATCH 12/14] S/390: arch13: vector shift double by bit builtins Date: Tue, 2 Apr 2019 13:20:59 +0200 In-Reply-To: <1554204061-30488-1-git-send-email-krebbel@linux.ibm.com> References: <1554204061-30488-1-git-send-email-krebbel@linux.ibm.com> Message-Id: <1554204061-30488-13-git-send-email-krebbel@linux.ibm.com>
Series	S/390: Add support for new cpu architecture - arch13. \| expand [Committed,00/14] S/390: Add support for new cpu architecture - arch13. [01/14] S/390: arch13: Add arch13 as architecture option [02/14] S/390: arch13: Support new bit operations [03/14] S/390: arch13: Support new popcount instruction variant. [04/14] S/390: arch13: Add support for new select instruction [05/14] S/390: arch13: Support 32 bit fp-int vector converts [06/14] S/390: arch13: Support 32 bit fp-int scalar converts [07/14] S/390: arch13: New vector builtins - preparation [08/14] S/390: arch13: vec_revb vector byte swap builtin [09/14] S/390: arch13: vec_reve element order reversal builtins [10/14] S/390: arch13: vector load/store byte reversed element for builtins [11/14] S/390: arch13: vector load byte reversed element and replicate [12/14] S/390: arch13: vector shift double by bit builtins [13/14] S/390: arch13: vector string search builtins [14/14] S/390: arch13: vector float-int conversion builtins

diff --git a/gcc/config/s390/s390-builtin-types.def b/gcc/config/s390/s390-builtin-types.def index ff53ec5..c0dd208 100644 --- a/gcc/config/s390/s390-builtin-types.def +++ b/gcc/config/s390/s390-builtin-types.def @@ -285,6 +285,7 @@ DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_INT, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_INT DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_INTPTR, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_INTPTR) DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_OV4SI, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_OV4SI) DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_UCHAR, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_UCHAR) +DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_UINT, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_UINT) DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_ULONGLONG, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_ULONGLONG) DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UCHAR_INT, BT_UV16QI, BT_UV16QI, BT_UCHAR, BT_INT) DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UV16QI_INT, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INT) @@ -513,6 +514,7 @@ DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_BV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_INT, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INT) DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INTPTR) DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UCHAR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UINT, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UINT) DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_ULONGLONG, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_ULONGLONG) DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI) DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INTPTR) @@ -544,6 +546,7 @@ DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI) DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_BV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_BV2DI) DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_INT, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_INT) DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_UCHAR, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_UINT, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UINT) DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_ULONGLONG, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_ULONGLONG) DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_ULONGLONGCONSTPTR_UCHAR, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_ULONGLONGCONSTPTR, BT_UCHAR) DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_UV16QI, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV16QI) @@ -581,6 +584,7 @@ DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_BV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_BV4 DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_INT, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INT) DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_INTPTR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INTPTR) DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UCHAR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UINT, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UINT) DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UINTCONSTPTR_UCHAR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UINTCONSTPTR, BT_UCHAR) DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_ULONGLONG, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_ULONGLONG) DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UV16QI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UV16QI) @@ -621,6 +625,7 @@ DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_BV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_BV8 DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_INT, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INT) DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_INTPTR, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INTPTR) DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UCHAR, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UCHAR) +DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UINT, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UINT) DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_ULONGLONG, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_ULONGLONG) DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UV16QI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV16QI) DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI) @@ -651,6 +656,7 @@ DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI, BT_V16QI, BT_V16QI, BT_V16QI) DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_BV16QI, BT_V16QI, BT_V16QI, BT_V16QI, BT_BV16QI) DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_INT, BT_V16QI, BT_V16QI, BT_V16QI, BT_INT) DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_INTPTR, BT_V16QI, BT_V16QI, BT_V16QI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_UINT, BT_V16QI, BT_V16QI, BT_V16QI, BT_UINT) DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_ULONGLONG, BT_V16QI, BT_V16QI, BT_V16QI, BT_ULONGLONG) DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_UV16QI, BT_V16QI, BT_V16QI, BT_V16QI, BT_UV16QI) DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_V16QI, BT_V16QI, BT_V16QI, BT_V16QI, BT_V16QI) @@ -675,6 +681,7 @@ DEF_OV_TYPE (BT_OV_V2DF_V2DF_UV2DI_DBLCONSTPTR_UCHAR, BT_V2DF, BT_V2DF, BT_UV2DI DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF, BT_V2DF, BT_V2DF, BT_V2DF) DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_BV2DI, BT_V2DF, BT_V2DF, BT_V2DF, BT_BV2DI) DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_INT, BT_V2DF, BT_V2DF, BT_V2DF, BT_INT) +DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_UINT, BT_V2DF, BT_V2DF, BT_V2DF, BT_UINT) DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_ULONGLONG, BT_V2DF, BT_V2DF, BT_V2DF, BT_ULONGLONG) DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_UV16QI, BT_V2DF, BT_V2DF, BT_V2DF, BT_UV16QI) DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_UV2DI, BT_V2DF, BT_V2DF, BT_V2DF, BT_UV2DI) @@ -705,6 +712,7 @@ DEF_OV_TYPE (BT_OV_V2DI_V2DI_UV8HI, BT_V2DI, BT_V2DI, BT_UV8HI) DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI, BT_V2DI, BT_V2DI, BT_V2DI) DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_BV2DI, BT_V2DI, BT_V2DI, BT_V2DI, BT_BV2DI) DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_INT, BT_V2DI, BT_V2DI, BT_V2DI, BT_INT) +DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_UINT, BT_V2DI, BT_V2DI, BT_V2DI, BT_UINT) DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_ULONGLONG, BT_V2DI, BT_V2DI, BT_V2DI, BT_ULONGLONG) DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_UV16QI, BT_V2DI, BT_V2DI, BT_V2DI, BT_UV16QI) DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_UV2DI, BT_V2DI, BT_V2DI, BT_V2DI, BT_UV2DI) @@ -728,6 +736,7 @@ DEF_OV_TYPE (BT_OV_V4SF_V4SF_UV4SI, BT_V4SF, BT_V4SF, BT_UV4SI) DEF_OV_TYPE (BT_OV_V4SF_V4SF_UV4SI_FLTCONSTPTR_UCHAR, BT_V4SF, BT_V4SF, BT_UV4SI, BT_FLTCONSTPTR, BT_UCHAR) DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF, BT_V4SF, BT_V4SF, BT_V4SF) DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_BV4SI, BT_V4SF, BT_V4SF, BT_V4SF, BT_BV4SI) +DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_UINT, BT_V4SF, BT_V4SF, BT_V4SF, BT_UINT) DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_ULONGLONG, BT_V4SF, BT_V4SF, BT_V4SF, BT_ULONGLONG) DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_UV16QI, BT_V4SF, BT_V4SF, BT_V4SF, BT_UV16QI) DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_UV4SI, BT_V4SF, BT_V4SF, BT_V4SF, BT_UV4SI) @@ -759,6 +768,7 @@ DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI, BT_V4SI, BT_V4SI, BT_V4SI) DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_BV4SI, BT_V4SI, BT_V4SI, BT_V4SI, BT_BV4SI) DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_INT, BT_V4SI, BT_V4SI, BT_V4SI, BT_INT) DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_INTPTR, BT_V4SI, BT_V4SI, BT_V4SI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_UINT, BT_V4SI, BT_V4SI, BT_V4SI, BT_UINT) DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_ULONGLONG, BT_V4SI, BT_V4SI, BT_V4SI, BT_ULONGLONG) DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_UV16QI, BT_V4SI, BT_V4SI, BT_V4SI, BT_UV16QI) DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_UV4SI, BT_V4SI, BT_V4SI, BT_V4SI, BT_UV4SI) @@ -794,6 +804,7 @@ DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI, BT_V8HI, BT_V8HI, BT_V8HI) DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_BV8HI, BT_V8HI, BT_V8HI, BT_V8HI, BT_BV8HI) DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_INT, BT_V8HI, BT_V8HI, BT_V8HI, BT_INT) DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_INTPTR, BT_V8HI, BT_V8HI, BT_V8HI, BT_INTPTR) +DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_UINT, BT_V8HI, BT_V8HI, BT_V8HI, BT_UINT) DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_ULONGLONG, BT_V8HI, BT_V8HI, BT_V8HI, BT_ULONGLONG) DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_UV16QI, BT_V8HI, BT_V8HI, BT_V8HI, BT_UV16QI) DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_UV8HI, BT_V8HI, BT_V8HI, BT_V8HI, BT_UV8HI) diff --git a/gcc/config/s390/s390-builtins.def b/gcc/config/s390/s390-builtins.def index e4cfa80..6ee921d 100644 --- a/gcc/config/s390/s390-builtins.def +++ b/gcc/config/s390/s390-builtins.def @@ -2923,3 +2923,31 @@ B_DEF (s390_vsterf, eltswapv4si, 0, B_DEF (s390_vsterg, eltswapv2di, 0, B_VX, 0, BT_FN_V2DI_V2DI) B_DEF (s390_vsterf_flt, eltswapv4sf, 0, B_VXE, 0, BT_FN_V4SF_V4SF) B_DEF (s390_vsterg_dbl, eltswapv2df, 0, B_VX, 0, BT_FN_V2DF_V2DF) + +OB_DEF (s390_vec_sldb, s390_vec_sldb_s8, s390_vec_sldb_dbl, B_VXE2, BT_FN_OV4SI_OV4SI_OV4SI_UINT) +OB_DEF_VAR (s390_vec_sldb_s8, s390_vsld, 0, O3_U3, BT_OV_V16QI_V16QI_V16QI_UINT) +OB_DEF_VAR (s390_vec_sldb_u8, s390_vsld, 0, O3_U3, BT_OV_UV16QI_UV16QI_UV16QI_UINT) +OB_DEF_VAR (s390_vec_sldb_s16, s390_vsld, 0, O3_U3, BT_OV_V8HI_V8HI_V8HI_UINT) +OB_DEF_VAR (s390_vec_sldb_u16, s390_vsld, 0, O3_U3, BT_OV_UV8HI_UV8HI_UV8HI_UINT) +OB_DEF_VAR (s390_vec_sldb_s32, s390_vsld, 0, O3_U3, BT_OV_V4SI_V4SI_V4SI_UINT) +OB_DEF_VAR (s390_vec_sldb_u32, s390_vsld, 0, O3_U3, BT_OV_UV4SI_UV4SI_UV4SI_UINT) +OB_DEF_VAR (s390_vec_sldb_s64, s390_vsld, 0, O3_U3, BT_OV_V2DI_V2DI_V2DI_UINT) +OB_DEF_VAR (s390_vec_sldb_u64, s390_vsld, 0, O3_U3, BT_OV_UV2DI_UV2DI_UV2DI_UINT) +OB_DEF_VAR (s390_vec_sldb_flt, s390_vsld, 0, O3_U3, BT_OV_V4SF_V4SF_V4SF_UINT) +OB_DEF_VAR (s390_vec_sldb_dbl, s390_vsld, 0, O3_U3, BT_OV_V2DF_V2DF_V2DF_UINT) + +B_DEF (s390_vsld, vec_sldbv16qi, 0, B_VXE2, O3_U3, BT_FN_UV16QI_UV16QI_UV16QI_INT) + +OB_DEF (s390_vec_srdb, s390_vec_srdb_s8, s390_vec_srdb_dbl, B_VXE2, BT_FN_OV4SI_OV4SI_OV4SI_UINT) +OB_DEF_VAR (s390_vec_srdb_s8, s390_vsrd, 0, O3_U3, BT_OV_V16QI_V16QI_V16QI_UINT) +OB_DEF_VAR (s390_vec_srdb_u8, s390_vsrd, 0, O3_U3, BT_OV_UV16QI_UV16QI_UV16QI_UINT) +OB_DEF_VAR (s390_vec_srdb_s16, s390_vsrd, 0, O3_U3, BT_OV_V8HI_V8HI_V8HI_UINT) +OB_DEF_VAR (s390_vec_srdb_u16, s390_vsrd, 0, O3_U3, BT_OV_UV8HI_UV8HI_UV8HI_UINT) +OB_DEF_VAR (s390_vec_srdb_s32, s390_vsrd, 0, O3_U3, BT_OV_V4SI_V4SI_V4SI_UINT) +OB_DEF_VAR (s390_vec_srdb_u32, s390_vsrd, 0, O3_U3, BT_OV_UV4SI_UV4SI_UV4SI_UINT) +OB_DEF_VAR (s390_vec_srdb_s64, s390_vsrd, 0, O3_U3, BT_OV_V2DI_V2DI_V2DI_UINT) +OB_DEF_VAR (s390_vec_srdb_u64, s390_vsrd, 0, O3_U3, BT_OV_UV2DI_UV2DI_UV2DI_UINT) +OB_DEF_VAR (s390_vec_srdb_flt, s390_vsrd, 0, O3_U3, BT_OV_V4SF_V4SF_V4SF_UINT) +OB_DEF_VAR (s390_vec_srdb_dbl, s390_vsrd, 0, O3_U3, BT_OV_V2DF_V2DF_V2DF_UINT) + +B_DEF (s390_vsrd, vec_srdbv16qi, 0, B_VXE2, O3_U3, BT_FN_UV16QI_UV16QI_UV16QI_INT) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index bdc7385..56ad11f 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -194,7 +194,9 @@ UNSPEC_VEC_RL_MASK UNSPEC_VEC_SLL UNSPEC_VEC_SLB - UNSPEC_VEC_SLDB + UNSPEC_VEC_SLDBYTE + UNSPEC_VEC_SLDBIT + UNSPEC_VEC_SRDBIT UNSPEC_VEC_SRAL UNSPEC_VEC_SRAB UNSPEC_VEC_SRL diff --git a/gcc/config/s390/vecintrin.h b/gcc/config/s390/vecintrin.h index 05707a1..fb60a77 100644 --- a/gcc/config/s390/vecintrin.h +++ b/gcc/config/s390/vecintrin.h @@ -327,4 +327,6 @@ __lcbb(const void *ptr, int bndry) #define vec_fp_test_data_class __builtin_s390_vec_fp_test_data_class #define vec_revb __builtin_s390_vec_revb #define vec_reve __builtin_s390_vec_reve +#define vec_sldb __builtin_s390_vec_sldb +#define vec_srdb __builtin_s390_vec_srdb #endif /* _VECINTRIN_H */ diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index 1595ffb..1c42d4e 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -1030,7 +1030,7 @@ (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v") (match_operand:V_HW 2 "register_operand" "v") (match_operand:QI 3 "const_int_operand" "C")] - UNSPEC_VEC_SLDB))] + UNSPEC_VEC_SLDBYTE))] "TARGET_VX" "vsldb\t%v0,%v1,%v2,%b3" [(set_attr "op_type" "VRI")]) @@ -1040,12 +1040,36 @@ (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "") (match_operand:V_HW 2 "register_operand" "") (match_operand:QI 3 "const_int_operand" "")] - UNSPEC_VEC_SLDB))] + UNSPEC_VEC_SLDBYTE))] "TARGET_VX" { operands[3] = GEN_INT (INTVAL (operands[3]) << 2); }) +; Vector shift left double by bit + +(define_insn "vec_sldb<mode>" + [(set (match_operand:V_HW 0 "register_operand" "=v") + (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v") + (match_operand:V_HW 2 "register_operand" "v") + (match_operand:QI 3 "const_int_operand" "C")] + UNSPEC_VEC_SLDBIT))] + "TARGET_VXE2" + "vsld\t%v0,%v1,%v2,%b3" + [(set_attr "op_type" "VRI")]) + +; Vector shift right double by bit + +(define_insn "vec_srdb<mode>" + [(set (match_operand:V_HW 0 "register_operand" "=v") + (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v") + (match_operand:V_HW 2 "register_operand" "v") + (match_operand:QI 3 "const_int_operand" "C")] + UNSPEC_VEC_SRDBIT))] + "TARGET_VXE2" + "vsrd\t%v0,%v1,%v2,%b3" + [(set_attr "op_type" "VRI")]) + ; Vector shift right arithmetic (define_insn "vec_sral<VI_HW:mode><VI_HW_QHS:mode>" diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-shift-left-double-by-bit-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec-shift-left-double-by-bit-1.c new file mode 100644 index 0000000..5fe1bb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-shift-left-double-by-bit-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=arch13 -mzvector -fno-asynchronous-unwind-tables -dp" } */ + +#include <vecintrin.h> + +vector unsigned char +foo1 (vector unsigned char a, vector unsigned char b) +{ + return vec_sldb (a, b, 0); +} + +vector signed char +foo2 (vector signed char a, vector signed char b) +{ + return vec_sldb (a, b, 1); +} + + +vector unsigned short +foo3 (vector unsigned short a, vector unsigned short b) +{ + return vec_sldb (a, b, 2); +} + +vector signed short +foo4 (vector signed short a, vector signed short b) +{ + return vec_sldb (a, b, 3); +} + +vector unsigned int +foo5 (vector unsigned int a, vector unsigned int *b) +{ + return vec_sldb (a, *b, 4); +} + +vector signed int +foo6 (vector signed int a, vector signed int b) +{ + return vec_sldb (a, b, 5); +} + + +vector unsigned long long +foo7 (vector unsigned long long a, vector unsigned long long b) +{ + return vec_sldb (a, (vector unsigned long long){ 1, 2 }, 6); +} + +vector signed long long +foo8 (vector signed long long a, vector signed long long b) +{ + return vec_sldb (a, b, 7); +} + + +vector float +foo9 (vector float a, vector float b) +{ + return vec_sldb (a, b, 1); +} + +vector double +foo10 (vector double a, vector double b) +{ + return vec_sldb (a, b, 3); +} + +/* { dg-final { scan-assembler-times "vsld" 10 } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-shift-right-double-by-bit-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec-shift-right-double-by-bit-1.c new file mode 100644 index 0000000..dce3b8a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-shift-right-double-by-bit-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=arch13 -mzvector -fno-asynchronous-unwind-tables -dp" } */ + +#include <vecintrin.h> + +vector unsigned char +foo1 (vector unsigned char a, vector unsigned char b) +{ + return vec_srdb (a, b, 0); +} + +vector signed char +foo2 (vector signed char a, vector signed char b) +{ + return vec_srdb (a, b, 1); +} + + +vector unsigned short +foo3 (vector unsigned short a, vector unsigned short b) +{ + return vec_srdb (a, b, 2); +} + +vector signed short +foo4 (vector signed short a, vector signed short b) +{ + return vec_srdb (a, b, 3); +} + +vector unsigned int +foo5 (vector unsigned int a, vector unsigned int *b) +{ + return vec_srdb (a, *b, 4); +} + +vector signed int +foo6 (vector signed int a, vector signed int b) +{ + return vec_srdb (a, b, 5); +} + + +vector unsigned long long +foo7 (vector unsigned long long a, vector unsigned long long b) +{ + return vec_srdb (a, (vector unsigned long long){ 1, 2 }, 6); +} + +vector signed long long +foo8 (vector signed long long a, vector signed long long b) +{ + return vec_srdb (a, b, 7); +} + + +vector float +foo9 (vector float a, vector float b) +{ + return vec_srdb (a, b, 1); +} + +vector double +foo10 (vector double a, vector double b) +{ + return vec_srdb (a, b, 3); +} + +/* { dg-final { scan-assembler-times "vsrd" 10 } } */

[12/14] S/390: arch13: vector shift double by bit builtins

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