diff mbox series

[11/14] S/390: arch13: vector load byte reversed element and replicate

Message ID 1554204061-30488-12-git-send-email-krebbel@linux.ibm.com
State New
Headers show
Series S/390: Add support for new cpu architecture - arch13. | expand

Commit Message

Andreas Krebbel April 2, 2019, 11:20 a.m. UTC 
gcc/ChangeLog:

2019-04-02  Andreas Krebbel  <krebbel@linux.ibm.com>

	("*vec_splats_bswap_vec<mode>", "*vec_splats_bswap_elem<mode>"):
	New insn definition.
	* config/s390/vx-builtins.md (V_HW_HSD): Move to ...
	* config/s390/vector.md (V_HW_HSD): ... here.

gcc/testsuite/ChangeLog:

2019-04-02  Andreas Krebbel  <krebbel@linux.ibm.com>

	* gcc.target/s390/zvector/replicate-bswap-1.c: New test.
	* gcc.target/s390/zvector/replicate-bswap-2.c: New test.
---
 gcc/config/s390/vector.md                          | 20 ++++++++++++++++
 gcc/config/s390/vx-builtins.md                     |  1 -
 .../gcc.target/s390/zvector/replicate-bswap-1.c    | 28 ++++++++++++++++++++++
 .../gcc.target/s390/zvector/replicate-bswap-2.c    | 28 ++++++++++++++++++++++
 4 files changed, 76 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-1.c
 create mode 100644 gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-2.c
diff mbox series

Patch

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index f25c866..8f02af4 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -34,6 +34,7 @@ 
 
 (define_mode_iterator V_HW_64 [V2DI V2DF])
 (define_mode_iterator VT_HW_HSDT [V8HI V4SI V4SF V2DI V2DF V1TI V1TF TI TF])
+(define_mode_iterator V_HW_HSD [V8HI V4SI (V4SF "TARGET_VXE") V2DI V2DF])
 
 ; Including TI for instructions that support it (va, vn, ...)
 (define_mode_iterator VT_HW [V16QI V8HI V4SI V2DI V2DF V1TI TI (V4SF "TARGET_VXE") (V1TF "TARGET_VXE")])
@@ -548,6 +549,25 @@ 
    #"
   [(set_attr "op_type" "VRX,VRI,VRI,*")])
 
+; vlbrreph, vlbrrepf, vlbrrepg
+(define_insn "*vec_splats_bswap_vec<mode>"
+  [(set (match_operand:V_HW_HSD                           0 "register_operand" "=v")
+	(bswap:V_HW_HSD
+	 (vec_duplicate:V_HW_HSD (match_operand:<non_vec> 1 "memory_operand"    "R"))))]
+  "TARGET_VXE2"
+  "vlbrrep<bhfgq>\t%v0,%1"
+  [(set_attr "op_type" "VRX")])
+
+; Why do we need both? Shouldn't there be a canonical form?
+; vlbrreph, vlbrrepf, vlbrrepg
+(define_insn "*vec_splats_bswap_elem<mode>"
+  [(set (match_operand:V_HW_HSD                    0 "register_operand" "=v")
+	(vec_duplicate:V_HW_HSD
+	 (bswap:<non_vec> (match_operand:<non_vec> 1 "memory_operand"    "R"))))]
+  "TARGET_VXE2"
+  "vlbrrep<bhfgq>\t%v0,%1"
+  [(set_attr "op_type" "VRX")])
+
 ; A TFmode operand resides in FPR register pairs while V1TF is in a
 ; single vector register.
 (define_insn "*vec_tf_to_v1tf"
diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md
index 8d837c4..1595ffb 100644
--- a/gcc/config/s390/vx-builtins.md
+++ b/gcc/config/s390/vx-builtins.md
@@ -22,7 +22,6 @@ 
 
 (define_mode_iterator V_HW_32_64 [V4SI V2DI V2DF (V4SF "TARGET_VXE")])
 (define_mode_iterator VI_HW_SD [V4SI V2DI])
-(define_mode_iterator V_HW_HSD [V8HI V4SI (V4SF "TARGET_VXE") V2DI V2DF])
 (define_mode_iterator V_HW_4 [V4SI V4SF])
 ; Full size vector modes with more than one element which are directly supported in vector registers by the hardware.
 (define_mode_iterator VEC_HW  [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE")])
diff --git a/gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-1.c b/gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-1.c
new file mode 100644
index 0000000..adecdb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-1.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O3 -mzarch -march=arch13 -mzvector -fno-asynchronous-unwind-tables -dp" } */
+
+#include <vecintrin.h>
+
+vector signed short
+vlbrreph (const signed short *a)
+{
+  return vec_revb (vec_splats (*a));
+}
+
+/* { dg-final { scan-assembler-times "vlbrreph.*\n\tvlbrreph.*vec_splats_bswap_vecv8hi" 1 } } */
+
+vector signed int
+vlbrrepf (const signed int *a)
+{
+  return vec_revb (vec_splats (*a));
+}
+
+/* { dg-final { scan-assembler-times "vlbrrepf.*\n\tvlbrrepf.*vec_splats_bswap_vecv4si" 1 } } */
+
+vector signed long long
+vlbrrepg (const signed long long *a)
+{
+  return vec_revb (vec_splats (*a));
+}
+
+/* { dg-final { scan-assembler-times "vlbrrepg.*\n\tvlbrrepg.*vec_splats_bswap_vecv2di" 1 } } */
diff --git a/gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-2.c b/gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-2.c
new file mode 100644
index 0000000..426dd54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-2.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O3 -mzarch -march=arch13 -mzvector -fno-asynchronous-unwind-tables -dp" } */
+
+#include <vecintrin.h>
+
+vector unsigned short
+vlbrreph (const unsigned short *a)
+{
+  return vec_splats (__builtin_bswap16 (*a));
+}
+
+/* { dg-final { scan-assembler-times "vlbrreph.*\n\tvlbrreph.*vec_splats_bswap_elemv8hi" 1 } } */
+
+vector unsigned int
+vlbrrepf (const unsigned int *a)
+{
+  return vec_splats (__builtin_bswap32 (*a));
+}
+
+/* { dg-final { scan-assembler-times "vlbrrepf.*\n\tvlbrrepf.*vec_splats_bswap_elemv4si" 1 } } */
+
+vector unsigned long long
+vlbrrepg (const unsigned long long *a)
+{
+  return vec_splats ((unsigned long long)__builtin_bswap64 (*a));
+}
+
+/* { dg-final { scan-assembler-times "vlbrrepg.*\n\tvlbrrepg.*vec_splats_bswap_elemv2di" 1 } } */