diff mbox series

[rs6000] Add vec_extract builtin tests, fix arguments on existing tests

Message ID 1529680895.7264.11.camel@us.ibm.com
State New
Headers show
Series [rs6000] Add vec_extract builtin tests, fix arguments on existing tests | expand

Commit Message

Carl Love June 22, 2018, 3:21 p.m. UTC 
GCC Maintainers:

The following patch adds tests for the vec_extract builtin.  I also
adjusts the second argument on the existing tests so they match the
ABI, specifically an integer not a const integer.

The patch has been tested on 

    powerpc64le-unknown-linux-gnu (Power 9 LE)
 
With no regressions.

Please let me know if the patch looks OK for GCC mainline. 

                         Carl Love

----------------------------------------------------------------

gcc/testsuite/ChangeLog:

2018-06-21  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/p9-extract-1.c: Make second argument of
 	vec_extract a signed int. Add vec_extract tests for bool char
	and bool int.
	* gcc.target/powerpc/p9-extract-4.c:  New test file for long long
	vec_extract tests.
---
 gcc/testsuite/gcc.target/powerpc/p9-extract-1.c | 52 +++++++++++++++++++------
 gcc/testsuite/gcc.target/powerpc/p9-extract-4.c | 30 ++++++++++++++
 2 files changed, 70 insertions(+), 12 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/p9-extract-4.c

Comments

Segher Boessenkool June 25, 2018, 9:27 a.m. UTC | #1 
Hi!

On Fri, Jun 22, 2018 at 08:21:35AM -0700, Carl Love wrote:
> GCC Maintainers:
> 
> The following patch adds tests for the vec_extract builtin.  I also
> adjusts the second argument on the existing tests so they match the
> ABI, specifically an integer not a const integer.

Does that make a difference anywhere?  It shouldn't as far as I know.

> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/p9-extract-4.c
> @@ -0,0 +1,30 @@
> +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */

powerpc*-*-* && lp64

> +/* This file tests the extraction of 64-bit values.  The direct move is
> +   prefered for the  64-bit extract as it is either lower latency or the same
> +   latency as the extract instruction depending on the Endianess of the system.
> +   Furthermore, there can be up to four move instructions in flight at a time
> +   versus only two extract intructions at a time.  */

Please say this is for Power9?  It won't stay true forever.

Okay for trunk with those trivial changes.  Thanks!


Segher
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/powerpc/p9-extract-1.c b/gcc/testsuite/gcc.target/powerpc/p9-extract-1.c
index ecbe0ed..ab9e766 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-extract-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-extract-1.c
@@ -13,84 +13,112 @@ 
 int
 extract_int_0 (vector int a)
 {
-  int b = vec_extract (a, 0);
+  int c = 0;
+  int b = vec_extract (a, c);
   return b;
 }
 
 int
 extract_int_3 (vector int a)
 {
-  int b = vec_extract (a, 3);
+  int c = 3;
+  int b = vec_extract (a, c);
   return b;
 }
 
 unsigned int
 extract_uint_0 (vector unsigned int a)
 {
-  unsigned int b = vec_extract (a, 0);
+  int c = 0;
+  unsigned int b = vec_extract (a, c);
   return b;
 }
 
 unsigned int
 extract_uint_3 (vector unsigned int a)
 {
-  unsigned int b = vec_extract (a, 3);
+  int c = 3;
+  unsigned int b = vec_extract (a, c);
   return b;
 }
 
 short
 extract_short_0 (vector short a)
 {
-  short b = vec_extract (a, 0);
+  int c = 0;
+  short b = vec_extract (a, c);
   return b;
 }
 
 short
 extract_short_7 (vector short a)
 {
-  short b = vec_extract (a, 7);
+  int c = 7;
+  short b = vec_extract (a, c);
   return b;
 }
 
 unsigned short
 extract_ushort_0 (vector unsigned short a)
 {
-  unsigned short b = vec_extract (a, 0);
+  int c = 0;
+  unsigned short b = vec_extract (a, c);
   return b;
 }
 
 unsigned short
 extract_ushort_7 (vector unsigned short a)
 {
-  unsigned short b = vec_extract (a, 7);
+  int c = 7;
+  unsigned short b = vec_extract (a, c);
   return b;
 }
 
 signed char
 extract_schar_0 (vector signed char a)
 {
-  signed char b = vec_extract (a, 0);
+  int c = 0;
+  signed char b = vec_extract (a, c);
   return b;
 }
 
 signed char
 extract_schar_15 (vector signed char a)
 {
-  signed char b = vec_extract (a, 15);
+  int c = 15;
+  signed char b = vec_extract (a, c);
   return b;
 }
 
 unsigned char
 extract_uchar_0 (vector unsigned char a)
 {
-  unsigned char b = vec_extract (a, 0);
+  int c = 0;
+  unsigned char b = vec_extract (a, c);
   return b;
 }
 
 unsigned char
 extract_uchar_15 (vector unsigned char a)
 {
-  signed char b = vec_extract (a, 15);
+  int c = 15;
+  signed char b = vec_extract (a, c);
+  return b;
+}
+
+unsigned char
+extract_bool_char_0 (vector bool char a)
+{
+  int c = 0;
+  unsigned char b = vec_extract (a, c);
+  return b;
+}
+
+unsigned int
+extract_bool_int_0 (vector bool int a)
+{
+  int c = 0;
+  unsigned int b = vec_extract (a, c);
   return b;
 }
 
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-extract-4.c b/gcc/testsuite/gcc.target/powerpc/p9-extract-4.c
new file mode 100644
index 0000000..5212949
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/p9-extract-4.c
@@ -0,0 +1,30 @@ 
+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+/* This file tests the extraction of 64-bit values.  The direct move is
+   prefered for the  64-bit extract as it is either lower latency or the same
+   latency as the extract instruction depending on the Endianess of the system.
+   Furthermore, there can be up to four move instructions in flight at a time
+   versus only two extract intructions at a time.  */
+
+#include <altivec.h>
+
+unsigned long long
+extract_bool_long_long_0 (vector bool long long a)
+{
+  int c = 0;
+  unsigned long long b = vec_extract (a, c);
+  return b;
+}
+
+unsigned long long int
+extract_long_long_0 (vector unsigned long long int a)
+{
+  int c = 0;
+  unsigned long long int b = vec_extract (a, c);
+  return b;
+}
+
+/* { dg-final { scan-assembler-times "m\[ft\]vsr" 2 } } */