From patchwork Sat Mar 31 02:57:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 893679 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-475665-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ph7yq3eP"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40Cjp84ms1z9s2b for ; Sat, 31 Mar 2018 13:57:33 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=uaV16Z63zKx3 K1Bl9wTeDW0AL8Clo3jg9VHithAUBfuoaIrRNhBWHKjT5KiIAUI3BF7SHVWEdMsG 581ee6/4dTw5u8hEA8xFjJpIWu+YFnLU7AhN3H7DWrB8Igy0kIRY0CmuUoSI99vJ 5w81xrP0647Al6jVwT0piv48k8x+h3g= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=gEe5cgOGCrHsZd8Utw yJtVIhCzo=; b=ph7yq3ePuQzGJoIYy0OGxBJuekMgVA2QEfizEowiuxCJhdJ3J3 AwOkkVKU6BicfrvJ26K4YUw/2WSY1AiTApBMZh0Myd6RQB+A/KG9dCCUuKtKYwTN c9qlZY0zjcmq7DKLZCzPLMbEtQW1gY0hRW22blTH5dojUYZ7ulW+mPwTc= Received: (qmail 28120 invoked by alias); 31 Mar 2018 02:57:26 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 28109 invoked by uid 89); 31 Mar 2018 02:57:24 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy= X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 31 Mar 2018 02:57:22 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 18CF41240891; Sat, 31 Mar 2018 02:57:21 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH] rs6000: Fix _mm_min_ps and _mm_max_ps (PR83315) Date: Sat, 31 Mar 2018 02:57:19 +0000 Message-Id: <1522465039-39208-1-git-send-email-segher@kernel.crashing.org> X-IsSubscribed: yes This makes _mm_{min,max}_ps work correctly for QNaNs. Tested on powerpc64le-linux; committing. Segher 2018-03-31 Segher Boessenkool PR target/83315 * config/rs6000/xmmintrin.h (_mm_set_ps, _mm_max_ps): Handle (quiet) NaN inputs correctly. gcc/testsuite/ PR target/83315 * gcc.target/powerpc/sse-maxps-2.c: New test. * gcc.target/powerpc/sse-minps-2.c: New test. --- gcc/config/rs6000/xmmintrin.h | 6 ++-- gcc/testsuite/gcc.target/powerpc/sse-maxps-2.c | 43 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/sse-minps-2.c | 43 ++++++++++++++++++++++++++ 3 files changed, 90 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/sse-maxps-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/sse-minps-2.c diff --git a/gcc/config/rs6000/xmmintrin.h b/gcc/config/rs6000/xmmintrin.h index 2cf2bf2..aa2823f 100644 --- a/gcc/config/rs6000/xmmintrin.h +++ b/gcc/config/rs6000/xmmintrin.h @@ -438,13 +438,15 @@ _mm_max_ss (__m128 __A, __m128 __B) extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_min_ps (__m128 __A, __m128 __B) { - return ((__m128)vec_min ((__v4sf)__A,(__v4sf) __B)); + __m128 m = (__m128) vec_vcmpgtfp ((__v4sf) __B, (__v4sf) __A); + return vec_sel (__B, __A, m); } extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_max_ps (__m128 __A, __m128 __B) { - return ((__m128)vec_max ((__v4sf)__A, (__v4sf)__B)); + __m128 m = (__m128) vec_vcmpgtfp ((__v4sf) __A, (__v4sf) __B); + return vec_sel (__B, __A, m); } /* Perform logical bit-wise operations on 128-bit values. */ diff --git a/gcc/testsuite/gcc.target/powerpc/sse-maxps-2.c b/gcc/testsuite/gcc.target/powerpc/sse-maxps-2.c new file mode 100644 index 0000000..5cf9c3f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/sse-maxps-2.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#include CHECK_H + +#ifndef TEST +#define TEST sse_test_maxps_2 +#endif + +#include + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_max_ps (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + int i; + + s1.x = _mm_set_ps (24.43, __builtin_nanf("1"), __builtin_nanf("2"), 546.46); + s2.x = _mm_set_ps (__builtin_nanf("3"), __builtin_nanf("4"), 3.15, 4.14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] > s2.a[i] ? s1.a[i] : s2.a[i]; + + if (__builtin_memcmp (&u, e, 16)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/sse-minps-2.c b/gcc/testsuite/gcc.target/powerpc/sse-minps-2.c new file mode 100644 index 0000000..4cb4b73 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/sse-minps-2.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#include CHECK_H + +#ifndef TEST +#define TEST sse_test_minps_2 +#endif + +#include + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_min_ps (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + int i; + + s1.x = _mm_set_ps (24.43, __builtin_nanf("1"), __builtin_nanf("2"), 546.46); + s2.x = _mm_set_ps (__builtin_nanf("3"), __builtin_nanf("4"), 3.15, 4.14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] < s2.a[i] ? s1.a[i] : s2.a[i]; + + if (__builtin_memcmp (&u, e, 16)) + abort (); +}