From patchwork Wed Feb 21 19:10:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Carl Love X-Patchwork-Id: 876246 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-473672-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="sL/sGir8"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zmnBX4xz9z9s00 for ; Thu, 22 Feb 2018 06:10:44 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:date:content-type:mime-version :content-transfer-encoding:message-id; q=dns; s=default; b=e/SRN JLthnnY8hfMTdHFQED9XnAOxCpI4Cob4apYXnlYZHpFhemFdMffa749rWWEXkQH0 TreL4GsuQRRHDiwDEEBmFKOr/z6PjFVaWKNetjb1OLvJdZE4SOUD3oRVjAyLS/1x YhEfQGUAaQ3A1KFO6YK1HnVnD5wubtmGP1M2vA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:date:content-type:mime-version :content-transfer-encoding:message-id; s=default; bh=GTiPwnBoqhG HDWvEKP1FMQ/BYOQ=; b=sL/sGir8VQxnQCRuk0nGLKXdfHRwujyuryTYMDKD4bj MoieUMzlm5+fzx1X8yqrPOOOgL3lXvYbfbUq5xa/mFxPeA7xfSkmZh7c1/BM+JpH BjQPRp6f/GIs0QJsdV14VHuwIrRnksUxtU+BJwWi85M4wzTlZ52XmvfmkwJwsstQ = Received: (qmail 119624 invoked by alias); 21 Feb 2018 19:10:37 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 119596 invoked by uid 89); 21 Feb 2018 19:10:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-27.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=2140, 2900 X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 21 Feb 2018 19:10:34 +0000 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w1LJ9iWI108180 for ; Wed, 21 Feb 2018 14:10:32 -0500 Received: from e33.co.us.ibm.com (e33.co.us.ibm.com [32.97.110.151]) by mx0a-001b2d01.pphosted.com with ESMTP id 2g9bcmh67q-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 21 Feb 2018 14:10:32 -0500 Received: from localhost by e33.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 21 Feb 2018 12:10:27 -0700 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w1LJARY912059034; Wed, 21 Feb 2018 12:10:27 -0700 Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 48C33136044; Wed, 21 Feb 2018 12:10:27 -0700 (MST) Received: from oc3304648336.ibm.com (unknown [9.80.232.180]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP id 2AF4E136040; Wed, 21 Feb 2018 12:10:26 -0700 (MST) Subject: [PATCH rs6000], Move Power 8 tests, fix ICE for vec_unsigned2, vec_signed2 From: Carl Love To: gcc-patches@gcc.gnu.org, David Edelsohn , Segher Boessenkool Cc: Bill Schmidt , cel@us.ibm.com Date: Wed, 21 Feb 2018 11:10:25 -0800 Mime-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 18022119-0008-0000-0000-0000095B70CE X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008571; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000254; SDB=6.00993080; UDB=6.00504579; IPR=6.00772424; MB=3.00019676; MTD=3.00000008; XFM=3.00000015; UTC=2018-02-21 19:10:29 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18022119-0009-0000-0000-0000461DA493 Message-Id: <1519240225.3293.5.camel@us.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-21_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1802210228 X-IsSubscribed: yes GCC maintainers: Per discussions with Segher, we felt it would be best to move the vec_float2 test to a Power 8 test as it is only defined for Power 8 and beyond. In doing this, I found that compiling builtins-3-runnable.c with -mcpu=power7 then generated an ICE for vec_signed2 and vec_unsigned2. It seems that once gcc saw the unsupported vec_float2 it exited with -mcpu=power7 it exited before seeing the vec_signed2 and vec_unsigned2 builtins. The vec_signed2 and vec_unsigned2 are also only defined for Power 8 and beyond. This patch moves the three power 8 builtins to a new test file builtins-3-runnable-p8.c. It also fixed the ICE by restricting the vec_signed2 and vec_unsigned2 builtins to Power 8. The builtins-3- runnable.c dg settings are then set to enable the test to run on Power 7. The patch has been tested on: powerpc64-unknown-linux-gnu (Power 8BE)  powerpc64le-unknown-linux-gnu (Power 8LE) powerpc64le-unknown-linux-gnu (Power 9LE) and no regressions were found. Additionally, the tests were compiled by hand with -mcpu=power7 to ensure gcc doesn't give and ICE. Please let me know if the patch looks OK or not. Thanks.                        Carl Love ------------------------------------------------------------------- gcc/ChangeLog: 2018-02-19 Carl Love * config/rs6000/rs6000-builtin.def: Change VSIGNED2 and VUNSIGNED2 macro expansions from BU_VSX_2 to BU_P8V_VSX_2 and BU_VSX_OVERLOAD_2 to BU_P8V_OVERLOAD_2. * config/rs6000/rs6000-c.c: Change VSX_BUILTIN_VEC_VSIGNED2 to P8V_BUILTIN_VEC_VSIGNED2. Change VSX_BUILTIN_VEC_VUNSIGNED2 to P8V_BUILTIN_VEC_VUNSIGNED2. gcc/testsuite/ChangeLog: 2018-02-19 Carl Love * gcc.target/powerpc/builtins-3-runnable.c: Move tests for vec_float2, vec_signed2 and vec_unsigned2 to new Power 8 test file. * gcc.target/powerpc/builtins-3-runnable-p8.c: New test file for Power 8 tests. --- gcc/config/rs6000/rs6000-builtin.def | 10 +- gcc/config/rs6000/rs6000-c.c | 4 +- .../gcc.target/powerpc/builtins-3-runnable-p8.c | 162 +++++++++++++++++++++ .../gcc.target/powerpc/builtins-3-runnable.c | 31 +--- 4 files changed, 170 insertions(+), 37 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-3-runnable-p8.c diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 876b1d9..f9548a0 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -1659,9 +1659,6 @@ BU_VSX_2 (CMPLE_U8HI, "cmple_u8hi", CONST, vector_ngtuv8hi) BU_VSX_2 (CMPLE_U4SI, "cmple_u4si", CONST, vector_ngtuv4si) BU_VSX_2 (CMPLE_U2DI, "cmple_u2di", CONST, vector_ngtuv2di) -BU_VSX_2 (VEC_VSIGNED2_V2DF, "vsigned2_v2df", CONST, vsigned2_v2df) -BU_VSX_2 (VEC_VUNSIGNED2_V2DF, "vunsigned2_v2df", CONST, vunsigned2_v2df) - /* VSX abs builtin functions. */ BU_VSX_A (XVABSDP, "xvabsdp", CONST, absv2df2) BU_VSX_A (XVNABSDP, "xvnabsdp", CONST, vsx_nabsv2df2) @@ -1852,8 +1849,6 @@ BU_VSX_OVERLOAD_2 (XXMRGHW, "xxmrghw") BU_VSX_OVERLOAD_2 (XXMRGLW, "xxmrglw") BU_VSX_OVERLOAD_2 (XXSPLTD, "xxspltd") BU_VSX_OVERLOAD_2 (XXSPLTW, "xxspltw") -BU_VSX_OVERLOAD_2 (VSIGNED2, "vsigned2") -BU_VSX_OVERLOAD_2 (VUNSIGNED2, "vunsigned2") /* 1 argument VSX overloaded builtin functions. */ BU_VSX_OVERLOAD_1 (DOUBLE, "double") @@ -1917,6 +1912,9 @@ BU_P8V_AV_1 (NEG_V2DF, "neg_v2df", CONST, negv2df2) BU_P8V_VSX_2 (FLOAT2_V2DF, "float2_v2df", CONST, float2_v2df) BU_P8V_VSX_2 (FLOAT2_V2DI, "float2_v2di", CONST, float2_v2di) BU_P8V_VSX_2 (UNS_FLOAT2_V2DI, "uns_float2_v2di", CONST, uns_float2_v2di) +BU_P8V_VSX_2 (VEC_VSIGNED2_V2DF, "vsigned2_v2df", CONST, vsigned2_v2df) +BU_P8V_VSX_2 (VEC_VUNSIGNED2_V2DF, "vunsigned2_v2df", CONST, vunsigned2_v2df) + /* 1 argument altivec instructions added in ISA 2.07. */ BU_P8V_AV_1 (ABS_V2DI, "abs_v2di", CONST, absv2di2) @@ -2063,6 +2061,8 @@ BU_P8V_OVERLOAD_2 (VSUBUDM, "vsubudm") BU_P8V_OVERLOAD_2 (VSUBUQM, "vsubuqm") BU_P8V_OVERLOAD_2 (FLOAT2, "float2") BU_P8V_OVERLOAD_2 (UNS_FLOAT2, "uns_float2") +BU_P8V_OVERLOAD_2 (VSIGNED2, "vsigned2") +BU_P8V_OVERLOAD_2 (VUNSIGNED2, "vunsigned2") /* ISA 2.07 vector overloaded 3 argument functions. */ BU_P8V_OVERLOAD_3 (VADDECUQ, "vaddecuq") diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 6e4a269..cc8e4e1 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -5876,7 +5876,7 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 }, { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF, RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 }, - { VSX_BUILTIN_VEC_VSIGNED2, VSX_BUILTIN_VEC_VSIGNED2_V2DF, + { P8V_BUILTIN_VEC_VSIGNED2, P8V_BUILTIN_VEC_VSIGNED2_V2DF, RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF, @@ -5887,7 +5887,7 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 }, { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 }, - { VSX_BUILTIN_VEC_VUNSIGNED2, VSX_BUILTIN_VEC_VUNSIGNED2_V2DF, + { P8V_BUILTIN_VEC_VUNSIGNED2, P8V_BUILTIN_VEC_VUNSIGNED2_V2DF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable-p8.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable-p8.c new file mode 100644 index 0000000..104ae55 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable-p8.c @@ -0,0 +1,162 @@ +/* { dg-do run { target { powerpc*-*-linux* && { p8vector_hw } } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=power8" } } */ +/* { dg-require-effective-target p8vector_hw } */ +/* { dg-options "-mcpu=power8" } */ + +#include // vector + +#ifdef DEBUG +#include +#endif + +#define ALL 1 +#define EVEN 2 +#define ODD 3 + +void abort (void); + +void test_int_result(int check, vector int vec_result, vector int vec_expected) +{ + int i; + + for (i = 0; i < 4; i++) { + switch (check) { + case ALL: + break; + case EVEN: + if (i%2 == 0) + break; + else + continue; + case ODD: + if (i%2 != 0) + break; + else + continue; + } + + if (vec_result[i] != vec_expected[i]) { +#ifdef DEBUG + printf("Test_int_result: "); + printf("vec_result[%d] (%d) != vec_expected[%d] (%d)\n", + i, vec_result[i], i, vec_expected[i]); +#else + abort(); +#endif + } + } +} + +void test_unsigned_int_result(int check, vector unsigned int vec_result, + vector unsigned int vec_expected) +{ + int i; + + for (i = 0; i < 4; i++) { + switch (check) { + case ALL: + break; + case EVEN: + if (i%2 == 0) + break; + else + continue; + case ODD: + if (i%2 != 0) + break; + else + continue; + } + + if (vec_result[i] != vec_expected[i]) { +#ifdef DEBUG + printf("Test_unsigned int_result: "); + printf("vec_result[%d] (%d) != vec_expected[%d] (%d)\n", + i, vec_result[i], i, vec_expected[i]); +#else + abort(); +#endif + } + + } +} + +void test_result_sp(int check, vector float vec_result, + vector float vec_expected) +{ + int i; + for(i = 0; i<4; i++) { + + switch (check) { + case ALL: + break; + case EVEN: + if (i%2 == 0) + break; + else + continue; + case ODD: + if (i%2 != 0) + break; + else + continue; + } + + if (vec_result[i] != vec_expected[i]) { +#ifdef DEBUG + printf("Test_result_sp: "); + printf("vec_result[%d] (%f) != vec_expected[%d] (%f)\n", + i, vec_result[i], i, vec_expected[i]); +#else + abort(); +#endif + } + } +} + +int main() +{ + int i; + vector unsigned int vec_unint, vec_uns_int_expected, vec_uns_int_result; + vector signed int vec_int, vec_int_expected, vec_int_result; + vector float vec_flt, vec_flt_result, vec_flt_expected; + vector long long int vec_ll_int0, vec_ll_int1; + vector long long unsigned int vec_ll_uns_int0, vec_ll_uns_int1; + vector double vec_dble0, vec_dble1, vec_dble_result, vec_dble_expected; + + vec_ll_int0 = (vector long long int){ -12, -12345678901234 }; + vec_ll_int1 = (vector long long int){ 12, 9876543210 }; + vec_ll_uns_int0 = (vector unsigned long long int){ 102, 9753108642 }; + vec_ll_uns_int1 = (vector unsigned long long int){ 23, 29 }; + + /* Convert two double precision vector float to vector int */ + vec_dble0 = (vector double){-124.930, 81234.49}; + vec_dble1 = (vector double){-24.370, 8354.99}; + vec_int_expected = (vector signed int){-124, 81234, -24, 8354}; + vec_int_result = vec_signed2 (vec_dble0, vec_dble1); + test_int_result (ALL, vec_int_result, vec_int_expected); + + /* Convert two double precision vector float to vector unsigned int */ + vec_dble0 = (vector double){124.930, 8134.49}; + vec_dble1 = (vector double){24.370, 834.99}; + vec_uns_int_expected = (vector unsigned int){124, 8134, 24, 834}; + vec_uns_int_result = vec_unsigned2 (vec_dble0, vec_dble1); + test_unsigned_int_result (ALL, vec_uns_int_result, + vec_uns_int_expected); + + /* conversion of two double precision vectors to single precision vector */ + vec_flt_expected = (vector float){-12.00, -12345678901234.00, 12.00, 9876543210.00}; + vec_flt_result = vec_float2 (vec_ll_int0, vec_ll_int1); + test_result_sp(ALL, vec_flt_result, vec_flt_expected); + + vec_flt_expected = (vector float){102.00, 9753108642.00, 23.00, 29.00}; + vec_flt_result = vec_float2 (vec_ll_uns_int0, vec_ll_uns_int1); + test_result_sp(ALL, vec_flt_result, vec_flt_expected); + + vec_dble0 = (vector double){ 34.0, 97.0 }; + vec_dble1 = (vector double){ 214.0, -5.5 }; + vec_flt_expected = (vector float){34.0, 97.0, 214.0, -5.5}; + vec_flt_result = vec_float2 (vec_dble0, vec_dble1); + test_result_sp(ALL, vec_flt_result, vec_flt_expected); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c index 43de454..b99bc36 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c @@ -1,7 +1,6 @@ /* { dg-do run { target { p8vector_hw } } } */ /* { dg-require-effective-target vsx_hw } */ -/* { dg-options "-O2 -mvsx -mcpu=power8" } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-maltivec -mvsx" } */ #include // vector @@ -257,19 +256,6 @@ int main() vec_flt_result = vec_float (vec_unint); test_result_sp(ALL, vec_flt_result, vec_flt_expected); - /* conversion of two double precision vectors to single precision vector */ - vec_flt_expected = (vector float){-12.00, -12345678901234.00, 12.00, 9876543210.00}; - vec_flt_result = vec_float2 (vec_ll_int0, vec_ll_int1); - test_result_sp(ALL, vec_flt_result, vec_flt_expected); - - vec_flt_expected = (vector float){102.00, 9753108642.00, 23.00, 29.00}; - vec_flt_result = vec_float2 (vec_ll_uns_int0, vec_ll_uns_int1); - test_result_sp(ALL, vec_flt_result, vec_flt_expected); - - vec_flt_expected = (vector float){34.0, 97.0, 214.0, -5.5}; - vec_flt_result = vec_float2 (vec_dble0, vec_dble1); - test_result_sp(ALL, vec_flt_result, vec_flt_expected); - /* conversion of even words in double precision vector to single precision vector */ vec_flt_expected = (vector float){-12.00, 00.00, -12345678901234.00, 0.00}; vec_flt_result = vec_floate (vec_ll_int0); @@ -308,13 +294,6 @@ int main() vec_ll_int_result = vec_signed (vec_dble0); test_ll_int_result (vec_ll_int_result, vec_ll_int_expected); - /* Convert two double precision vector float to vector int */ - vec_dble0 = (vector double){-124.930, 81234.49}; - vec_dble1 = (vector double){-24.370, 8354.99}; - vec_int_expected = (vector signed int){-124, 81234, -24, 8354}; - vec_int_result = vec_signed2 (vec_dble0, vec_dble1); - test_int_result (ALL, vec_int_result, vec_int_expected); - /* Convert double precision vector float to vector int, even words */ vec_dble0 = (vector double){-124.930, 81234.49}; vec_int_expected = (vector signed int){-124, 0, 81234, 0}; @@ -334,14 +313,6 @@ int main() test_ll_unsigned_int_result (vec_ll_uns_int_result, vec_ll_uns_int_expected); - /* Convert two double precision vector float to vector unsigned int */ - vec_dble0 = (vector double){124.930, 8134.49}; - vec_dble1 = (vector double){24.370, 834.99}; - vec_uns_int_expected = (vector unsigned int){124, 8134, 24, 834}; - vec_uns_int_result = vec_unsigned2 (vec_dble0, vec_dble1); - test_unsigned_int_result (ALL, vec_uns_int_result, - vec_uns_int_expected); - /* Convert double precision vector float to vector unsigned int, even words */ vec_dble0 = (vector double){3124.930, 8234.49};