| Message ID | 1511780999-27757-4-git-send-email-claziss@synopsys.com |
|---|---|
| State | New |
| Headers | show |
| Series | Critical fixes | expand |
* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-11-27 12:09:52 +0100]: > From: Claudiu Zissulescu <claziss@gmail.com> > > The ARC ZOL implementation doesn't allow the last instruction to be a > control instruction or part of a delay slot. Thus, we add a note to > the last ZOL instruction which will prevent it to finish into a delay > slot. > > 2017-10-20 Claudiu Zissulescu <claziss@synopsys.com> > > * config/arc/arc.c (hwloop_optimize): Prevent the last > ZOL instruction to end into a delay slot. > * config/arc/arc.md (cond_delay_insn): Check if the instruction > can be placed into a delay slot against reg_note. > (in_delay_slot): Likewise. > > testsuite/ > 2017-10-20 Claudiu Zissulescu <claziss@synopsys.com> > > * gcc.target/arc/loop-3.c: New test. > * gcc.target/arc/loop-4.c: Likewise. OK. Thanks, Andrew > > [FIX][ZOL] fix checking for jumps > --- > gcc/config/arc/arc.c | 6 ++++++ > gcc/config/arc/arc.md | 4 ++++ > gcc/testsuite/gcc.target/arc/loop-3.c | 27 +++++++++++++++++++++++++++ > gcc/testsuite/gcc.target/arc/loop-4.c | 14 ++++++++++++++ > 4 files changed, 51 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/arc/loop-3.c > create mode 100644 gcc/testsuite/gcc.target/arc/loop-4.c > > diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c > index 964815a..1479a8d 100644 > --- a/gcc/config/arc/arc.c > +++ b/gcc/config/arc/arc.c > @@ -7609,6 +7609,12 @@ hwloop_optimize (hwloop_info loop) > loop->loop_no); > last_insn = emit_insn_after (gen_nopv (), last_insn); > } > + > + /* SAVE_NOTE is used by haifa scheduler. However, we are after it > + and we can use it to indicate the last ZOL instruction cannot be > + part of a delay slot. */ > + add_reg_note (last_insn, REG_SAVE_NOTE, GEN_INT (2)); > + > loop->last_insn = last_insn; > > /* Get the loop iteration register. */ > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index 2e0ac52..6239483 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -472,6 +472,8 @@ > (symbol_ref "(arc_hazard (prev_active_insn (insn), insn) > + arc_hazard (insn, next_active_insn (insn)))")) > (const_string "false") > + (match_test "find_reg_note (insn, REG_SAVE_NOTE, GEN_INT (2))") > + (const_string "false") > (eq_attr "iscompact" "maybe") (const_string "true") > ] > > @@ -499,6 +501,8 @@ > (cond [(eq_attr "cond" "!canuse") (const_string "no") > (eq_attr "type" "call,branch,uncond_branch,jump,brcc") > (const_string "no") > + (match_test "find_reg_note (insn, REG_SAVE_NOTE, GEN_INT (2))") > + (const_string "no") > (eq_attr "length" "2,4") (const_string "yes")] > (const_string "no"))) > > diff --git a/gcc/testsuite/gcc.target/arc/loop-3.c b/gcc/testsuite/gcc.target/arc/loop-3.c > new file mode 100644 > index 0000000..bf7aec9 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arc/loop-3.c > @@ -0,0 +1,27 @@ > +/* { dg-do assemble } */ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mno-sdata" } * > + > +/* This example will fail to assemble if the last instruction is a > + branch with delay slot. */ > +int d; > +extern char * fn2 (void); > + > +void fn1(void) > +{ > + char *a = fn2(); > + for (;;) { > + long long b; > + int e = 8; > + for (; e <= 63; e += 7) { > + long c = *a++; > + b += c & e; > + if (c & 28) > + break; > + } > + d = b; > + } > +} > + > +/* { dg-final { scan-assembler "bne_s @.L2" } } */ > +/* { dg-final { scan-assembler-not "add.eq" } } */ > diff --git a/gcc/testsuite/gcc.target/arc/loop-4.c b/gcc/testsuite/gcc.target/arc/loop-4.c > new file mode 100644 > index 0000000..99a93a7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arc/loop-4.c > @@ -0,0 +1,14 @@ > +/* { dg-do assemble } */ > +/* { dg-do compile } */ > +/* { dg-options "-Os" } */ > + > + > +void fn1(void *p1, int p2, int p3) > +{ > + char *d = p1; > + do > + *d++ = p2; > + while (--p3); > +} > + > +/* { dg-final { scan-assembler "lp_count" } } */ > -- > 1.9.1 >
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 964815a..1479a8d 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -7609,6 +7609,12 @@ hwloop_optimize (hwloop_info loop) loop->loop_no); last_insn = emit_insn_after (gen_nopv (), last_insn); } + + /* SAVE_NOTE is used by haifa scheduler. However, we are after it + and we can use it to indicate the last ZOL instruction cannot be + part of a delay slot. */ + add_reg_note (last_insn, REG_SAVE_NOTE, GEN_INT (2)); + loop->last_insn = last_insn; /* Get the loop iteration register. */ diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 2e0ac52..6239483 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -472,6 +472,8 @@ (symbol_ref "(arc_hazard (prev_active_insn (insn), insn) + arc_hazard (insn, next_active_insn (insn)))")) (const_string "false") + (match_test "find_reg_note (insn, REG_SAVE_NOTE, GEN_INT (2))") + (const_string "false") (eq_attr "iscompact" "maybe") (const_string "true") ] @@ -499,6 +501,8 @@ (cond [(eq_attr "cond" "!canuse") (const_string "no") (eq_attr "type" "call,branch,uncond_branch,jump,brcc") (const_string "no") + (match_test "find_reg_note (insn, REG_SAVE_NOTE, GEN_INT (2))") + (const_string "no") (eq_attr "length" "2,4") (const_string "yes")] (const_string "no"))) diff --git a/gcc/testsuite/gcc.target/arc/loop-3.c b/gcc/testsuite/gcc.target/arc/loop-3.c new file mode 100644 index 0000000..bf7aec9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/loop-3.c @@ -0,0 +1,27 @@ +/* { dg-do assemble } */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-sdata" } * + +/* This example will fail to assemble if the last instruction is a + branch with delay slot. */ +int d; +extern char * fn2 (void); + +void fn1(void) +{ + char *a = fn2(); + for (;;) { + long long b; + int e = 8; + for (; e <= 63; e += 7) { + long c = *a++; + b += c & e; + if (c & 28) + break; + } + d = b; + } +} + +/* { dg-final { scan-assembler "bne_s @.L2" } } */ +/* { dg-final { scan-assembler-not "add.eq" } } */ diff --git a/gcc/testsuite/gcc.target/arc/loop-4.c b/gcc/testsuite/gcc.target/arc/loop-4.c new file mode 100644 index 0000000..99a93a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/loop-4.c @@ -0,0 +1,14 @@ +/* { dg-do assemble } */ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ + + +void fn1(void *p1, int p2, int p3) +{ + char *d = p1; + do + *d++ = p2; + while (--p3); +} + +/* { dg-final { scan-assembler "lp_count" } } */
From: Claudiu Zissulescu <claziss@gmail.com> The ARC ZOL implementation doesn't allow the last instruction to be a control instruction or part of a delay slot. Thus, we add a note to the last ZOL instruction which will prevent it to finish into a delay slot. 2017-10-20 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (hwloop_optimize): Prevent the last ZOL instruction to end into a delay slot. * config/arc/arc.md (cond_delay_insn): Check if the instruction can be placed into a delay slot against reg_note. (in_delay_slot): Likewise. testsuite/ 2017-10-20 Claudiu Zissulescu <claziss@synopsys.com> * gcc.target/arc/loop-3.c: New test. * gcc.target/arc/loop-4.c: Likewise. [FIX][ZOL] fix checking for jumps --- gcc/config/arc/arc.c | 6 ++++++ gcc/config/arc/arc.md | 4 ++++ gcc/testsuite/gcc.target/arc/loop-3.c | 27 +++++++++++++++++++++++++++ gcc/testsuite/gcc.target/arc/loop-4.c | 14 ++++++++++++++ 4 files changed, 51 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arc/loop-3.c create mode 100644 gcc/testsuite/gcc.target/arc/loop-4.c