From patchwork Wed Nov 8 05:12:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre McCurdy X-Patchwork-Id: 835592 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-466202-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="CAzeOUt/"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yWvh23Rb4z9sMN for ; Wed, 8 Nov 2017 16:17:52 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=Lr5APnp/SJ5B 5zpgwgWQ8P7IyNxObTMpjY15vySpO6RWWJsMNV2nIDQ1uAkX1jf/OXIp6aQu+jLf CR+n+iMLdtJShcZ7ciiqe1UHQOqYyevwlhu4K+ZjxWrGNgXRxRWrAZlAR3jJKF+J cWjB7xFCN6hVYaOKD1Xp1ImOq9wVYGw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=kbFzsyaJVVP81i++m+ VrPwJ76ls=; b=CAzeOUt/x9wHlGn7zHIPxH91KMJmB1ZJlALDBptlQi9rjVG+LT 6G8p59UXnPltW1I6ApdrqoJhKi8GRezYa9Od6loKIcXASwgh89bosWJThSFBkmXt iwVEUirpab7LCWeAGEPlueA59DZOBN8FrUH3+wdxVPvcVTQ4n+a5iJTSU= Received: (qmail 80400 invoked by alias); 8 Nov 2017 05:17:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59753 invoked by uid 89); 8 Nov 2017 05:15:55 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.4 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=xxx X-HELO: mail-pg0-f68.google.com Received: from mail-pg0-f68.google.com (HELO mail-pg0-f68.google.com) (74.125.83.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 08 Nov 2017 05:12:53 +0000 Received: by mail-pg0-f68.google.com with SMTP id s2so1087226pge.10 for ; Tue, 07 Nov 2017 21:12:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ROBm/VaZ9OjYp1waw1piXLe/MIUtnZLiIky7LMPDe0s=; b=WUrSQAXbw1u52FTcOYVK2Rjg6756PFlGLLKRinlP566hHqVS0cmW1uJdZhFKue2W+z 79GbzqccPRpWHZA1RktkJmoD1phri04gizQsawS0tcDobR5fhRjWlK1CVYBNGqZo7jG4 gJFG6o41iqVz55PBKy1nU8n4Jiv7eXSW7B/0vJNJbVcP0y6ifFJhKjtUDlu5WV1OTS7n 5Zv9stP5WzLvZHRkBfB5/G6oS84neUhAGS6M81TihCQAZ39K8aOXCIiqhEh4bUyID9R/ 4w/H9FHD8kRbOy2jXLcUSLLGsx1mM/umYUQO/TKgv2Ay0S/0pt4GMrVnINzUtHTd4zLA sewQ== X-Gm-Message-State: AJaThX7tjwjgr5VbqpB1McetmhKgnoj/KtyqUXGqtvxeRLFiirlFYJWb ya3bktQPgJ8l9qnN3YzGBZcSKQ== X-Google-Smtp-Source: ABhQp+TeUr2oCntJUeoL3qfMEovaSWZqKm9nB1+mWtyjChi+1Hf2d0NDqFD7WtqTWsGb9n1QzTejrQ== X-Received: by 10.99.109.79 with SMTP id i76mr1159597pgc.134.1510117971787; Tue, 07 Nov 2017 21:12:51 -0800 (PST) Received: from e6520.guest-wifi.scl.liberty.com ([4.16.80.121]) by smtp.gmail.com with ESMTPSA id n72sm5824787pfi.92.2017.11.07.21.12.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Nov 2017 21:12:50 -0800 (PST) From: Andre McCurdy To: gcc-patches@gcc.gnu.org Cc: Andre McCurdy Subject: [GCC-6.4][ARM][PATCH] enable FL_LPAE flag for armv7ve cores Date: Tue, 7 Nov 2017 21:12:44 -0800 Message-Id: <1510117964-4895-1-git-send-email-armccurdy@gmail.com> The following commit added the FL_LPAE flag to FL_FOR_ARCH7VE, but neglected to also add it to the armv7ve compatible cores defined in arm-cores.def. https://github.com/gcc-mirror/gcc/commit/af2d9b9e58e8be576c53d94f30c48c68146b0c98 The result is that gcc 6.4 now refuses to allow -march=armv7ve and -mcpu=XXX to be used together, even when -mcpu is set to an armv7ve compatible core: arm-linux-gnueabi-gcc -march=armv7ve -mcpu=cortex-a7 -Werror ... error: switch -mcpu=cortex-a7 conflicts with -march=armv7ve switch [-Werror] This is a regression relative to gcc 6.3. Fix by defining flags for armv7ve compatible cores directly from FL_FOR_ARCH7VE, rather than re-creating the armv7ve flags independently by combining FL_FOR_ARCH7A with the armv7ve specific FL_THUMB_DIV and FL_ARM_DIV flags. Signed-off-by: Andre McCurdy --- gcc/config/arm/arm-cores.def | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 829b839..ca37e6f 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -145,12 +145,12 @@ ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus, /* V7 Architecture Processors */ ARM_CORE("generic-armv7-a", genericv7a, genericv7a, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex) ARM_CORE("cortex-a5", cortexa5, cortexa5, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a5) -ARM_CORE("cortex-a7", cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7) +ARM_CORE("cortex-a7", cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a7) ARM_CORE("cortex-a8", cortexa8, cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a8) ARM_CORE("cortex-a9", cortexa9, cortexa9, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a9) -ARM_CORE("cortex-a12", cortexa12, cortexa17, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) -ARM_CORE("cortex-a15", cortexa15, cortexa15, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15) -ARM_CORE("cortex-a17", cortexa17, cortexa17, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) +ARM_CORE("cortex-a12", cortexa12, cortexa17, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a12) +ARM_CORE("cortex-a15", cortexa15, cortexa15, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a15) +ARM_CORE("cortex-a17", cortexa17, cortexa17, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a12) ARM_CORE("cortex-r4", cortexr4, cortexr4, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex) ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex) ARM_CORE("cortex-r5", cortexr5, cortexr5, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex) @@ -162,8 +162,8 @@ ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), marvell_pj4) /* V7 big.LITTLE implementations */ -ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15) -ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) +ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a15) +ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7VE), cortex_a12) /* V8 Architecture Processors */ ARM_CORE("cortex-a32", cortexa32, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)