From patchwork Tue Sep 12 08:34:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charles Baylis X-Patchwork-Id: 812720 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-461893-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="k8OvcsiY"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xrym74htzz9s81 for ; Tue, 12 Sep 2017 18:35:19 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=GlLRsrZN6t8iS7Qn8tdRGycBHo7Ign6vX8IUYpHaO5nn4QQTELGQ7 eBTtOEmNqdcNOf0WGqrEResdwLI0kz6ukNbUoc/U8xzSdR5dbQxgr8qn2iUzHqQy Azcm5EcKZXG+mgG+ktKlwhhQmKJeQgR/PVrrGvu11+4Y2eXripaxYM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=OrvdAY4DMXMhy98nR0B3Uy8HUD4=; b=k8OvcsiYdJFKzlM9+5J9 BG1Y6nIuXIcbfK+e/Mx1JShTuQN3Cv6SkR4cf8Ln1FtREgRR4jpBjPJxKbfwDHYs g0INve0w/whL4FnXg2trandFuJeSl0sbJ4rSIq2j0Hb6Aj6KXh2V8TrMUTNtn0h4 r6nEUQ/V7dj/50Pbcc9hyac= Received: (qmail 74987 invoked by alias); 12 Sep 2017 08:34:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 74890 invoked by uid 89); 12 Sep 2017 08:34:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=sk:charles X-HELO: mail-wr0-f172.google.com Received: from mail-wr0-f172.google.com (HELO mail-wr0-f172.google.com) (209.85.128.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 12 Sep 2017 08:34:55 +0000 Received: by mail-wr0-f172.google.com with SMTP id m18so19037963wrm.2 for ; Tue, 12 Sep 2017 01:34:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=//UwRE2ND77guwTYUG3tcO2LhAn9wAAvlnwex+hmMq4=; b=P4yNHi/PbaYRxka9M5vZJyeJvXDHlxBVi61ENLZ/ex2H8So/dmvgvcmRcEoxkyraJy DWD2PFuijLayohqfVsehXwMDujjPSbKhk4CpGIFqy/uqKDQe+zznCwA6u2D5S2vApFaC YON74OIKzRCy5FOAmre4L88BVLiJ/fkFya30DcVIlmdVnUDJD1nUbB95AxguR80wv18h eK3H3+74ugYGhI+xtcPNaZA6IW2kkIZP0XY6PJAmoODT5t4OlNNVHw6dCXUcbK6zoBv5 qNARLzAOLt5TQZZXS8CKi5gFFf3Slt4270322EEDUKTQ47p3WiLnvwcnN/BVsTA3mb6w ce3A== X-Gm-Message-State: AHPjjUgnNJv9rvuttJZ5sbNV9KAFbdDdP9RlEKmNIM4i7FPctDRfLYeR PTpY4xrRSoKpfdtW X-Google-Smtp-Source: ADKCNb4kfqZB7oSnkZeZ0u9hutwxZtsy+HyAnl1sYdbjc9N+C/ZO4l6NA8xM8hv9qmqELAoxMtGSyw== X-Received: by 10.223.170.202 with SMTP id i10mr11500880wrc.232.1505205293363; Tue, 12 Sep 2017 01:34:53 -0700 (PDT) Received: from localhost.localdomain (cpc92322-cmbg19-2-0-cust1928.5-4.cable.virginm.net. [86.26.39.137]) by smtp.gmail.com with ESMTPSA id s126sm13321227wmd.46.2017.09.12.01.34.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Sep 2017 01:34:52 -0700 (PDT) From: charles.baylis@linaro.org To: rearnsha@arm.com, Ramana.Radhakrishnan@arm.com, pinskia@gmail.com, kyrylo.tkachov@arm.com Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 1/3] [ARM] Add bus_width_bits to tune_params Date: Tue, 12 Sep 2017 09:34:35 +0100 Message-Id: <1505205277-26276-2-git-send-email-charles.baylis@linaro.org> In-Reply-To: <1505205277-26276-1-git-send-email-charles.baylis@linaro.org> References: <1505205277-26276-1-git-send-email-charles.baylis@linaro.org> X-IsSubscribed: yes From: Charles Baylis Add bus widths. These use the approximation that v7 and later cores have 64bit data bus width, and earlier cores have 32 bit bus width, with the exception of v7m. Charles Baylis * config/arm/arm-protos.h (struct tune_params): New field bus_width. * config/arm/arm.c (arm_slowmul_tune): Initialise bus_width field. (arm_fastmul_tune): Likewise. (arm_strongarm_tune): Likewise. (arm_xscale_tune): Likewise. (arm_9e_tune): Likewise. (arm_marvell_pj4_tune): Likewise. (arm_v6t2_tune): Likewise. (arm_cortex_tune): Likewise. (arm_cortex_a8_tune): Likewise. (arm_cortex_a7_tune): Likewise. (arm_cortex_a15_tune): Likewise. (arm_cortex_a35_tune): Likewise. (arm_cortex_a53_tune): Likewise. (arm_cortex_a57_tune): Likewise. (arm_exynosm1_tune): Likewise. (arm_xgene1_tune): Likewise. (arm_cortex_a5_tune): Likewise. (arm_cortex_a9_tune): Likewise. (arm_cortex_a12_tune): Likewise. (arm_cortex_a73_tune): Likewise. (arm_v7m_tune): Likewise. (arm_cortex_m7_tune): Likewise. (arm_v6m_tune): Likewise. (arm_fa726te_tune): Likewise. Change-Id: I613e876db93ffd6f8c1e72ba483be2efc0b56d66 --- gcc/config/arm/arm-protos.h | 2 ++ gcc/config/arm/arm.c | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 4538078..47a85cc 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -278,6 +278,8 @@ struct tune_params int max_insns_inline_memset; /* Issue rate of the processor. */ unsigned int issue_rate; + /* Bus width (bits). */ + unsigned int bus_width; /* Explicit prefetch data. */ struct { diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index bca8a34..32001e5 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1761,6 +1761,7 @@ const struct tune_params arm_slowmul_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -1783,6 +1784,7 @@ const struct tune_params arm_fastmul_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -1808,6 +1810,7 @@ const struct tune_params arm_strongarm_tune = 3, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -1830,6 +1833,7 @@ const struct tune_params arm_xscale_tune = 3, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -1852,6 +1856,7 @@ const struct tune_params arm_9e_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -1874,6 +1879,7 @@ const struct tune_params arm_marvell_pj4_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -1896,6 +1902,7 @@ const struct tune_params arm_v6t2_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -1920,6 +1927,7 @@ const struct tune_params arm_cortex_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -1942,6 +1950,7 @@ const struct tune_params arm_cortex_a8_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -1964,6 +1973,7 @@ const struct tune_params arm_cortex_a7_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -1986,6 +1996,7 @@ const struct tune_params arm_cortex_a15_tune = 2, /* Max cond insns. */ 8, /* Memset max inline. */ 3, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_TRUE, @@ -2008,6 +2019,7 @@ const struct tune_params arm_cortex_a35_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -2030,6 +2042,7 @@ const struct tune_params arm_cortex_a53_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -2052,6 +2065,7 @@ const struct tune_params arm_cortex_a57_tune = 2, /* Max cond insns. */ 8, /* Memset max inline. */ 3, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_TRUE, @@ -2074,6 +2088,7 @@ const struct tune_params arm_exynosm1_tune = 2, /* Max cond insns. */ 8, /* Memset max inline. */ 3, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_TRUE, @@ -2096,6 +2111,7 @@ const struct tune_params arm_xgene1_tune = 2, /* Max cond insns. */ 32, /* Memset max inline. */ 4, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_TRUE, @@ -2121,6 +2137,7 @@ const struct tune_params arm_cortex_a5_tune = 1, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -2143,6 +2160,7 @@ const struct tune_params arm_cortex_a9_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_BENEFICIAL(4,32,32), tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -2165,6 +2183,7 @@ const struct tune_params arm_cortex_a12_tune = 2, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_TRUE, @@ -2187,6 +2206,7 @@ const struct tune_params arm_cortex_a73_tune = 2, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_TRUE, @@ -2216,6 +2236,7 @@ const struct tune_params arm_v7m_tune = 2, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -2240,6 +2261,7 @@ const struct tune_params arm_cortex_m7_tune = 1, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -2265,6 +2287,7 @@ const struct tune_params arm_v6m_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -2287,6 +2310,7 @@ const struct tune_params arm_fa726te_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE,