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Violators will be prosecuted for from ; Tue, 22 Aug 2017 13:03:07 -0600 Received: from b03cxnp08026.gho.boulder.ibm.com (9.17.130.18) by e35.co.us.ibm.com (192.168.1.135) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Tue, 22 Aug 2017 13:03:04 -0600 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v7MJ34ao63045834; Tue, 22 Aug 2017 12:03:04 -0700 Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4BF097803F; Tue, 22 Aug 2017 13:03:04 -0600 (MDT) Received: from [9.10.86.107] (unknown [9.10.86.107]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP id E09AB78038; Tue, 22 Aug 2017 13:03:03 -0600 (MDT) Subject: [PATCH, rs6000] (v2) Testcase coverage for vec_perm built-ins From: Will Schmidt Reply-To: will_schmidt@vnet.ibm.com To: GCC Patches Cc: Segher Boessenkool , "Carl E. Love" , Bill Schmidt , David Edelsohn In-Reply-To: <1502979563.14827.10.camel@brimstone.rchland.ibm.com> References: <1502979563.14827.10.camel@brimstone.rchland.ibm.com> Date: Tue, 22 Aug 2017 14:03:03 -0500 Mime-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 17082219-0012-0000-0000-000014E54573 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007592; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000223; SDB=6.00906124; UDB=6.00454128; IPR=6.00686326; BA=6.00005550; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016815; XFM=3.00000015; UTC=2017-08-22 19:03:06 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17082219-0013-0000-0000-00004F2F3123 Message-Id: <1503428583.14827.28.camel@brimstone.rchland.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-08-22_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1708220291 X-IsSubscribed: yes Hi, [PATCH, rs6000] (v2) Testcase coverage for vec_perm built-ins Add some Testcase coverage for the vector permute intrinsics. (v2) Revisited and reworked all of the requires statements throughout this batch. Everything specifies -maltivec except the double and long long tests, which require vsx. (re-) Tested across power platforms. OK for trunk? Thanks, -Will [gcc/testsuite] 2017-08-17 Will Schmidt * gcc.target/powerpc/fold-vec-perm-char.c: New. * gcc.target/powerpc/fold-vec-perm-double.c: New. * gcc.target/powerpc/fold-vec-perm-float.c: New. * gcc.target/powerpc/fold-vec-perm-int.c: New. * gcc.target/powerpc/fold-vec-perm-longlong.c: New. * gcc.target/powerpc/fold-vec-perm-pixel.c: New. * gcc.target/powerpc/fold-vec-perm-short.c: New. diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-char.c new file mode 100644 index 0000000..d907eae --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-char.c @@ -0,0 +1,31 @@ +/* Verify that overloaded built-ins for vec_perm with char + inputs produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector bool char +testbc (vector bool char vbc2, vector bool char vbc3, + vector unsigned char vuc) +{ + return vec_perm (vbc2, vbc3, vuc); +} + +vector signed char +testsc (vector signed char vsc2, vector signed char vsc3, + vector unsigned char vuc) +{ + return vec_perm (vsc2, vsc3, vuc); +} + +vector unsigned char +testuc (vector unsigned char vuc2, vector unsigned char vuc3, + vector unsigned char vuc) +{ + return vec_perm (vuc2, vuc3, vuc); +} + +/* { dg-final { scan-assembler-times "vperm" 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-double.c new file mode 100644 index 0000000..7ceca9e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-double.c @@ -0,0 +1,17 @@ +/* Verify that overloaded built-ins for vec_perm with double + inputs produce the right code. */ + +/* { dg-do compile } */ +// vector double needs -mvsx. +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include + +vector double +testd (vector double vd2, vector double vd3, vector unsigned char vuc) +{ + return vec_perm (vd2, vd3, vuc); +} + +/* { dg-final { scan-assembler-times "vperm" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-float.c new file mode 100644 index 0000000..c9cfb0d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-float.c @@ -0,0 +1,16 @@ +/* Verify that overloaded built-ins for vec_perm with float + inputs produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector float +testf (vector float vf2, vector float vf3, vector unsigned char vuc) +{ + return vec_perm (vf2, vf3, vuc); +} + +/* { dg-final { scan-assembler-times "vperm" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-int.c new file mode 100644 index 0000000..a2fdc26 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-int.c @@ -0,0 +1,31 @@ +/* Verify that overloaded built-ins for vec_perm with int + inputs produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector bool int +testbi (vector bool int vbi2, vector bool int vbi3, + vector unsigned char vuc) +{ + return vec_perm (vbi2, vbi3, vuc); +} + +vector signed int +testsi (vector signed int vsi2, vector signed int vsi3, + vector unsigned char vuc) +{ + return vec_perm (vsi2, vsi3, vuc); +} + +vector unsigned int +testui (vector unsigned int vui2, vector unsigned int vui3, + vector unsigned char vuc) +{ + return vec_perm (vui2, vui3, vuc); +} + +/* { dg-final { scan-assembler-times "vperm" 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-longlong.c new file mode 100644 index 0000000..7f3e574 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-longlong.c @@ -0,0 +1,32 @@ +/* Verify that overloaded built-ins for vec_perm with long long + inputs produce the right code. */ + +/* { dg-do compile {target lp64} } */ +// 'long long' in Altivec types is invalid without -mvsx. +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include + +vector bool long long +testbl (vector bool long long vbl2, vector bool long long vbl3, + vector unsigned char vuc) +{ + return vec_perm (vbl2, vbl3, vuc); +} + +vector signed long long +testsl (vector signed long vsl2, vector signed long vsl3, + vector unsigned char vuc) +{ + return vec_perm (vsl2, vsl3, vuc); +} + +vector unsigned long long +testul (vector unsigned long long vul2, vector unsigned long long vul3, + vector unsigned char vuc) +{ + return vec_perm (vul2, vul3, vuc); +} + +/* { dg-final { scan-assembler-times "vperm" 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-pixel.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-pixel.c new file mode 100644 index 0000000..0d3cb0a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-pixel.c @@ -0,0 +1,16 @@ +/* Verify that overloaded built-ins for vec_perm with pixel + inputs produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector pixel +testpx (vector pixel px2, vector pixel px3, vector unsigned char vuc) +{ + return vec_perm (px2, px3, vuc); +} + +/* { dg-final { scan-assembler-times "vperm" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-short.c new file mode 100644 index 0000000..de5303a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-perm-short.c @@ -0,0 +1,29 @@ +/* Verify that overloaded built-ins for vec_perm with short + inputs produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector bool short +testbs (vector bool short vbs2, vector bool short vbs3, + vector unsigned char vuc) +{ + return vec_perm (vbs2, vbs3, vuc); +} + +vector signed short +testss (vector signed short vss2, vector signed short vss3, vector unsigned char vuc) +{ + return vec_perm (vss2, vss3, vuc); +} + +vector unsigned short +testus (vector unsigned short vus2, vector unsigned short vus3, vector unsigned char vuc) +{ + return vec_perm (vus2, vus3, vuc); +} + +/* { dg-final { scan-assembler-times "vperm" 3 } } */