From patchwork Thu Jun 1 13:34:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu X-Patchwork-Id: 769746 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wdpNR2hMjz9s78 for ; Thu, 1 Jun 2017 23:39:17 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="pJ5qCtA+"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=U0L0RYM8y+eSgN+t 5Frwlm/mRqkviDH/T9h2rQpioapKpRxglQBDnlo+y2DIhHHnlyVyujlvxUt0OGSL s9J9EmkQjUvTPxoHQXYPszCqUGzc+xZBTkIdYydNw353coVYHZ+POc2RkfezO8BT 11h7Bw/F12fojVblNYIIr+Z4/eo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=2E+Rp5RUpWtOlpCeKlWCVl rQ1Q8=; b=pJ5qCtA+nwwBxsONqU/Y9GFGT1/a00/InVX9KT7wZUALYFvogSMRR1 WEXaKZm82yDDfwcxaeOLIV5J0hz1RjKAAbf07xzJg39YAb50hlbu8tNYZ2RhnNVq jJ2YJhWtoZu4wPQxw8/DcvAeoknK9Yh9/EkBb4NgReY2nHxcI3H18= Received: (qmail 97656 invoked by alias); 1 Jun 2017 13:37:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 97549 invoked by uid 89); 1 Jun 2017 13:37:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-23.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy= X-HELO: smtprelay.synopsys.com Received: from smtprelay.synopsys.com (HELO smtprelay.synopsys.com) (198.182.47.9) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 01 Jun 2017 13:37:56 +0000 Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by smtprelay.synopsys.com (Postfix) with ESMTP id 6758A24E2044; Thu, 1 Jun 2017 06:37:59 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 51130EB4; Thu, 1 Jun 2017 06:37:59 -0700 (PDT) Received: from US01WXQAHTC1.internal.synopsys.com (us01wxqahtc1.internal.synopsys.com [10.12.238.230]) by mailhost.synopsys.com (Postfix) with ESMTP id 47F69EB1; Thu, 1 Jun 2017 06:37:59 -0700 (PDT) Received: from IN01WEHTCB.internal.synopsys.com (10.144.199.106) by US01WXQAHTC1.internal.synopsys.com (10.12.238.230) with Microsoft SMTP Server (TLS) id 14.3.266.1; Thu, 1 Jun 2017 06:37:59 -0700 Received: from IN01WEHTCA.internal.synopsys.com (10.144.199.104) by IN01WEHTCB.internal.synopsys.com (10.144.199.105) with Microsoft SMTP Server (TLS) id 14.3.266.1; Thu, 1 Jun 2017 19:07:57 +0530 Received: from nl20droid1.internal.synopsys.com (10.100.24.228) by IN01WEHTCA.internal.synopsys.com (10.144.199.243) with Microsoft SMTP Server (TLS) id 14.3.266.1; Thu, 1 Jun 2017 19:07:57 +0530 From: Claudiu Zissulescu To: CC: , , Subject: [PATCH 4/7] [ARC] [LRA] Avoid emitting COND_EXEC during expand. Date: Thu, 1 Jun 2017 15:34:54 +0200 Message-ID: <1496324097-21221-5-git-send-email-claziss@synopsys.com> In-Reply-To: <1496324097-21221-1-git-send-email-claziss@synopsys.com> References: <1496324097-21221-1-git-send-email-claziss@synopsys.com> MIME-Version: 1.0 Emmitting COND_EXEC rtxes during expand does not always work. gcc/ 2017-01-10 Claudiu Zissulescu * config/arc/arc.md (clzsi2): Expand to an arc_clzsi2 instruction that also clobbers the CC register. The old expand code is moved to ... (*arc_clzsi2): ... here. (ctzsi2): Expand to an arc_ctzsi2 instruction that also clobbers the CC register. The old expand code is moved to ... (arc_ctzsi2): ... here. --- gcc/config/arc/arc.md | 41 ++++++++++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 7 deletions(-) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 39bcc26..928feb1 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -4533,9 +4533,21 @@ (set_attr "type" "two_cycle_core,two_cycle_core")]) (define_expand "clzsi2" - [(set (match_operand:SI 0 "dest_reg_operand" "") - (clz:SI (match_operand:SI 1 "register_operand" "")))] + [(parallel + [(set (match_operand:SI 0 "register_operand" "") + (clz:SI (match_operand:SI 1 "register_operand" ""))) + (clobber (match_dup 2))])] + "TARGET_NORM" + "operands[2] = gen_rtx_REG (CC_ZNmode, CC_REG);") + +(define_insn_and_split "*arc_clzsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (clz:SI (match_operand:SI 1 "register_operand" "r"))) + (clobber (reg:CC_ZN CC_REG))] "TARGET_NORM" + "#" + "reload_completed" + [(const_int 0)] { emit_insn (gen_norm_f (operands[0], operands[1])); emit_insn @@ -4552,9 +4564,23 @@ }) (define_expand "ctzsi2" - [(set (match_operand:SI 0 "register_operand" "") - (ctz:SI (match_operand:SI 1 "register_operand" "")))] + [(match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "register_operand" "")] "TARGET_NORM" + " + emit_insn (gen_arc_ctzsi2 (operands[0], operands[1])); + DONE; +") + +(define_insn_and_split "arc_ctzsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (ctz:SI (match_operand:SI 1 "register_operand" "r"))) + (clobber (reg:CC_ZN CC_REG)) + (clobber (match_scratch:SI 2 "=&r"))] + "TARGET_NORM" + "#" + "reload_completed" + [(const_int 0)] { rtx temp = operands[0]; @@ -4562,10 +4588,10 @@ || (REGNO (temp) < FIRST_PSEUDO_REGISTER && !TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], REGNO (temp)))) - temp = gen_reg_rtx (SImode); + temp = operands[2]; emit_insn (gen_addsi3 (temp, operands[1], constm1_rtx)); emit_insn (gen_bic_f_zn (temp, temp, operands[1])); - emit_insn (gen_clrsbsi2 (temp, temp)); + emit_insn (gen_clrsbsi2 (operands[0], temp)); emit_insn (gen_rtx_COND_EXEC (VOIDmode, @@ -4575,7 +4601,8 @@ (gen_rtx_COND_EXEC (VOIDmode, gen_rtx_GE (VOIDmode, gen_rtx_REG (CC_ZNmode, CC_REG), const0_rtx), - gen_rtx_SET (operands[0], gen_rtx_MINUS (SImode, GEN_INT (31), temp)))); + gen_rtx_SET (operands[0], gen_rtx_MINUS (SImode, GEN_INT (31), + operands[0])))); DONE; })