diff mbox

[rs6000] Add vec_nabs builtin support

Message ID 1484332079.14851.11.camel@us.ibm.com
State New
Headers show

Commit Message

Carl Love Jan. 13, 2017, 6:27 p.m. UTC 
Segar:

The issues you pointed out below have been addressed in the following
updated patch.  Please let me know if the changes are acceptable.
Thanks for your help and feedback.

                       Carl Love
> rs6000-c.c
> 
> > 	vector signed char vec_nabs (vector signed char)
> > 	vector signed short vec_nabs (vector signed short)
> > 	vector signed int vec_nabs (vector signed int)
> > 	vector signed long long vec_nabs (vector signed long long)
> > 	vector float vec_nabs (vector float)
> > 	vector double vec_nabs (vector double)
> 
> You should mention the name of the function or data etc. you modified here:

> 	rs6000-c.c (altivec_overloaded_builtins): Blabla.
> 
> or something like that.
> 
> > 	* config/rs6000/rs6000-builtin.def: Add definitions for NABS functions
> > 	and NABS overload.
> > 	* config/rs6000/altivec.md: Add define to expand nabs<mode>2 types
> > 	* config/rs6000/altivec.h: Add define for vec_nabs built-in function.
> > 	* doc/extend.texi: Update the built-in documentation file for the
> > 	new built-in functions.
> 
> Here, too.
> 
> > +  int i, n_elt = GET_MODE_NUNITS (<MODE>mode);
> 
> Two lines for this please, two separate declarations.  I realise you just
> copied this code ;-)
--------------------------------------------------------------------------------------

gcc/ChangeLog:

2017-01-08  Carl Love  <cel@us.ibm.com>

	* config/rs6000/rs6000-c (altivec_overloaded_builtins): Add support
	for built-in functions
	vector signed char vec_nabs (vector signed char)
	vector signed short vec_nabs (vector signed short)
	vector signed int vec_nabs (vector signed int)
	vector signed long long vec_nabs (vector signed long long)
	vector float vec_nabs (vector float)
	vector double vec_nabs (vector double)
	* config/rs6000/rs6000-builtin.def: Add definitions for NABS functions
	and NABS overload.
	* config/rs6000/altivec.md: Add define to expand nabs<mode>2 types
	* config/rs6000/altivec.h: Add define for vec_nabs built-in function.
	* doc/extend.texi (section 6.60.22 PowerPC AltiVec Built-in Functions):
	Update the documentation file for the new built-in functions.

gcc/testsuite/ChangeLog:

2017-01-08  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/builtins-3.c: Add tests for the new built-ins
	to the test suite file.
	* gcc.target/powerpc/builtins-3-p8.c: Add tests for the new built-ins
	to the test suite file.
---
 gcc/config/rs6000/altivec.h                      |  1 +
 gcc/config/rs6000/altivec.md                     | 27 ++++++++++++++
 gcc/config/rs6000/rs6000-builtin.def             |  9 +++++
 gcc/config/rs6000/rs6000-c.c                     | 12 ++++++
 gcc/doc/extend.texi                              |  8 ++++
 gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c | 12 +++++-
 gcc/testsuite/gcc.target/powerpc/builtins-3.c    | 47 +++++++++++++++++++++++-
 7 files changed, 114 insertions(+), 2 deletions(-)

Comments

Segher Boessenkool Jan. 14, 2017, 10:32 a.m. UTC | #1 
Hi Carl,

On Fri, Jan 13, 2017 at 10:27:59AM -0800, Carl E. Love wrote:
> 	* config/rs6000/altivec.md: Add define to expand nabs<mode>2 types

* config/rs6000/altivec.md (nabs<mode>2): New define_expand.

> 	* doc/extend.texi (section 6.60.22 PowerPC AltiVec Built-in Functions):
> 	Update the documentation file for the new built-in functions.

Section numbers aren't stable (or in the source file at all), just remove
it here.

> 2017-01-08  Carl Love  <cel@us.ibm.com>
> 
> 	* gcc.target/powerpc/builtins-3.c: Add tests for the new built-ins
> 	to the test suite file.
> 	* gcc.target/powerpc/builtins-3-p8.c: Add tests for the new built-ins
> 	to the test suite file.

Just say "New.", "New testcase.", or "New file.".  New <anything> is much
easier to write changelog entries for than modified <something> ;-)

Okay for trunk with those changes.  Thanks!


Segher
diff mbox

Patch

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 73567ff..17bc33e 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -189,6 +189,7 @@ 
 #define vec_vupklsh __builtin_vec_vupklsh
 #define vec_vupklsb __builtin_vec_vupklsb
 #define vec_abs __builtin_vec_abs
+#define vec_nabs __builtin_vec_nabs
 #define vec_abss __builtin_vec_abss
 #define vec_add __builtin_vec_add
 #define vec_adds __builtin_vec_adds
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index c2063d5..2a26007 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2741,6 +2741,33 @@ 
 })
 
 ;; Generate
+;;    vspltisw SCRATCH1,0
+;;    vsubu?m SCRATCH2,SCRATCH1,%1
+;;    vmins? %0,%1,SCRATCH2"
+(define_expand "nabs<mode>2"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 4)
+        (minus:VI2 (match_dup 2)
+		   (match_operand:VI2 1 "register_operand" "v")))
+   (set (match_operand:VI2 0 "register_operand" "=v")
+        (smin:VI2 (match_dup 1) (match_dup 4)))]
+  "<VI_unit>"
+{
+  int i;
+  int n_elt = GET_MODE_NUNITS (<MODE>mode);
+
+  rtvec v = rtvec_alloc (n_elt);
+
+  /* Create an all 0 constant.  */
+  for (i = 0; i < n_elt; ++i)
+    RTVEC_ELT (v, i) = const0_rtx;
+
+  operands[2] = gen_reg_rtx (<MODE>mode);
+  operands[3] = gen_rtx_CONST_VECTOR (<MODE>mode, v);
+  operands[4] = gen_reg_rtx (<MODE>mode);
+})
+
+;; Generate
 ;;    vspltisw SCRATCH1,-1
 ;;    vslw SCRATCH2,SCRATCH1,SCRATCH1
 ;;    vandc %0,%1,SCRATCH2
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 2329c1f..1cdf9a8 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1129,6 +1129,14 @@  BU_ALTIVEC_A (ABSS_V4SI,      "abss_v4si",	SAT,	altivec_abss_v4si)
 BU_ALTIVEC_A (ABSS_V8HI,      "abss_v8hi",	SAT,	altivec_abss_v8hi)
 BU_ALTIVEC_A (ABSS_V16QI,     "abss_v16qi",	SAT,	altivec_abss_v16qi)
 
+/* Altivec NABS functions.  */
+BU_ALTIVEC_A (NABS_V2DI,      "nabs_v2di",	CONST,	nabsv2di2)
+BU_ALTIVEC_A (NABS_V4SI,      "nabs_v4si",	CONST,	nabsv4si2)
+BU_ALTIVEC_A (NABS_V8HI,      "nabs_v8hi",	CONST,	nabsv8hi2)
+BU_ALTIVEC_A (NABS_V16QI,     "nabs_v16qi",	CONST,	nabsv16qi2)
+BU_ALTIVEC_A (NABS_V4SF,      "nabs_v4sf",	CONST,	vsx_nabsv4sf2)
+BU_ALTIVEC_A (NABS_V2DF,      "nabs_v2df",	CONST,	vsx_nabsv2df2)
+
 /* 1 argument Altivec builtin functions.  */
 BU_ALTIVEC_1 (VEXPTEFP,	      "vexptefp",	FP,	altivec_vexptefp)
 BU_ALTIVEC_1 (VLOGEFP,	      "vlogefp",	FP,	altivec_vlogefp)
@@ -1408,6 +1416,7 @@  BU_ALTIVEC_OVERLOAD_2 (XOR,	   "xor")
 
 /* 1 argument Altivec overloaded functions.  */
 BU_ALTIVEC_OVERLOAD_1 (ABS,	   "abs")
+BU_ALTIVEC_OVERLOAD_1 (NABS,	   "nabs")
 BU_ALTIVEC_OVERLOAD_1 (ABSS,	   "abss")
 BU_ALTIVEC_OVERLOAD_1 (CEIL,	   "ceil")
 BU_ALTIVEC_OVERLOAD_1 (EXPTE,	   "expte")
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index b928547..3bc1f73 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -1992,6 +1992,18 @@  const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB,
     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
+  { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI,
+    RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI,
+    RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI,
+    RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI,
+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF,
+    RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP,
+    RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI,
     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 6be113c..f8864eb 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -16304,6 +16304,12 @@  vector unsigned short vec_vmuloub (vector unsigned char,
 
 vector float vec_nmsub (vector float, vector float, vector float);
 
+vector signed char vec_nabs (vector signed char);
+vector signed short vec_nabs (vector signed short);
+vector signed int vec_nabs (vector signed int);
+vector float vec_nabs (vector float);
+vector double vec_nabs (vector double);
+
 vector float vec_nor (vector float, vector float);
 vector signed int vec_nor (vector signed int, vector signed int);
 vector unsigned int vec_nor (vector unsigned int, vector unsigned int);
@@ -17710,6 +17716,8 @@  vector long long vec_min (vector long long, vector long long);
 vector unsigned long long vec_min (vector unsigned long long,
                                    vector unsigned long long);
 
+vector signed long long vec_nabs (vector signed long long);
+
 vector long long vec_nand (vector long long, vector long long);
 vector long long vec_nand (vector bool long long, vector long long);
 vector long long vec_nand (vector long long, vector bool long long);
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
index 8acdd89..d2964b4 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
@@ -16,10 +16,20 @@  test_pack_float (vector double x, vector double y)
   return vec_pack (x, y);
 }
 
+vector long long
+test_nabs_long_long (vector long long x)
+{
+  return vec_nabs (x);
+}
+
 /* Expected test results:
 
      test_eq_long_long          1 vcmpequd inst
-     test_pack_float            1 vpkudum inst */
+     test_pack_float            1 vpkudum inst
+     test_nabs_long_long        1 vspltisw, 1 vsubudm, 1 vminsd */
 
 /* { dg-final { scan-assembler-times "vcmpequd" 1 } } */
 /* { dg-final { scan-assembler-times "vpkudum"  1 } } */
+/* { dg-final { scan-assembler-times "vspltisw" 1 } } */
+/* { dg-final { scan-assembler-times "vsubudm"  1 } } */
+/* { dg-final { scan-assembler-times "vminsd"   1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3.c b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
index f070bf3..bddd0ac 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
@@ -28,14 +28,59 @@  test_shift_left_double (vector double x, vector double y)
 	return vec_sld (x, y, /* shift_by */ 10);
 }
 
+vector signed char
+test_nabs_char (vector signed char x)
+{
+	return vec_nabs (x);
+}
+
+vector short
+test_nabs_short (vector short x)
+{
+  return vec_nabs (x);
+}
+
+vector int
+test_nabs_int (vector int x)
+{
+  return vec_nabs (x);
+}
+
+vector float
+test_nabs_float (vector float x)
+{
+  return vec_nabs (x);
+}
+
+vector double
+test_nabs_double (vector double x)
+{
+	return vec_nabs (x);
+}
+
 /* Expected test results:
 
      test_eq_char              1 vcmpequb inst
      test_eq_short             1 vcmpequh inst
      test_eq_int               1 vcmpequw inst
-     test_shift_left_double    1 vsldoi inst */
+     test_shift_left_double    1 vsldoi inst
+     test_nabs_char            1 vspltisw, 1 vsububm, 1 vminsb
+     test_nabs_short           1 vspltisw, 1 vsubuhm, 1 vminsh
+     test_nabs_int             1 vspltisw, 1 vsubuwm, 1 vminsw
+     test_nabs_float           1 xvnabssp
+     test_nabs_double          1 xvnabsdp */
 
 /* { dg-final { scan-assembler-times "vcmpequb" 1 } } */
 /* { dg-final { scan-assembler-times "vcmpequh" 1 } } */
 /* { dg-final { scan-assembler-times "vcmpequw" 1 } } */
 /* { dg-final { scan-assembler-times "vsldoi"   1 } } */
+/* { dg-final { scan-assembler-times "vsububm"  1 } } */
+/* { dg-final { scan-assembler-times "vsubuhm"  1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm"  1 } } */
+/* { dg-final { scan-assembler-times "vminsb"   1 } } */
+/* { dg-final { scan-assembler-times "vminsh"   1 } } */
+/* { dg-final { scan-assembler-times "vminsw"   1 } } */
+/* { dg-final { scan-assembler-times "vspltisw" 3 } } */
+/* { dg-final { scan-assembler-times "xvnabssp" 1 } } */
+/* { dg-final { scan-assembler-times "xvnabsdp" 1 } } */
+