From patchwork Mon Dec 19 17:01:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: will schmidt X-Patchwork-Id: 707162 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tj6dT3pLTz9syB for ; Tue, 20 Dec 2016 04:01:33 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="LGzGzFkp"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:reply-to:to:cc:content-type:date:mime-version :content-transfer-encoding:message-id; q=dns; s=default; b=xSQnk YT/t0UCJ1N+uI1vPjPoz4guMkTUlWyL1pdi/76VBBgOFoj+BCQ5+pxW7r653zh+A rm+EjjHLU9ZkdXThYSutgWPDlbatZOYZsvUm79Ga6pQiiGHPdiXaCh/WI+1n+weh XJdUGLgMM9ttV388wqDuHfozDdJ3i2whdgbCs8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:reply-to:to:cc:content-type:date:mime-version :content-transfer-encoding:message-id; s=default; bh=TjmYNUjSNhy D3rxFk6secj03MrQ=; b=LGzGzFkpuwQOQo1PwI+JzF0f+hg3+YiHVsN8VssRuR0 hmBur8fnOI8uj7OmmUIuzsDed00VQKIn3ePcZ+dx8ZNoIgnQaRffW5MPj++rUfRF cHdtj7p0RdEKnocD9wheqexV6MoG+ij7WGGGLAa7WxCIaTPwmCiP0jtYo3QfwDlE = Received: (qmail 75305 invoked by alias); 19 Dec 2016 17:01:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 75282 invoked by uid 89); 19 Dec 2016 17:01:20 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=rs6000c, rs6000.c, sk:rs6000_, UD:rs6000.c X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 19 Dec 2016 17:01:18 +0000 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id uBJGwtPg106633 for ; Mon, 19 Dec 2016 12:01:16 -0500 Received: from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150]) by mx0b-001b2d01.pphosted.com with ESMTP id 27efv5779m-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 19 Dec 2016 12:01:16 -0500 Received: from localhost by e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 19 Dec 2016 10:01:10 -0700 Received: from b03cxnp08027.gho.boulder.ibm.com (b03cxnp08027.gho.boulder.ibm.com [9.17.130.19]) by d03dlp02.boulder.ibm.com (Postfix) with ESMTP id 905163E40054; Mon, 19 Dec 2016 10:01:09 -0700 (MST) Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id uBJH19qN5505456; Mon, 19 Dec 2016 10:01:09 -0700 Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 752F478051; Mon, 19 Dec 2016 10:01:09 -0700 (MST) Received: from [9.10.86.107] (unknown [9.10.86.107]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP id 1D1EA7803F; Mon, 19 Dec 2016 10:01:09 -0700 (MST) Subject: [PATCH, rs6000] Fold vector subtract built-ins in GIMPLE From: Will Schmidt Reply-To: will_schmidt@vnet.ibm.com To: GCC Patches Cc: Bill Schmidt , David Edelsohn , Segher Boessenkool Date: Mon, 19 Dec 2016 11:01:08 -0600 Mime-Version: 1.0 X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16121917-0004-0000-0000-0000111F51B7 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006279; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000198; SDB=6.00796077; UDB=6.00386318; IPR=6.00573891; BA=6.00004986; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00013658; XFM=3.00000011; UTC=2016-12-19 17:01:14 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16121917-0005-0000-0000-00007B893CB0 Message-Id: <1482166868.13393.53.camel@brimstone.rchland.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-12-19_14:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1612190209 X-IsSubscribed: yes Hi, This patch implements folding of the vector subtract built-ins. This follows the form used by Bill in his previous "Fold vector addition built-ins in GIMPLE" patch. :-) Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no regressions. Is this ok for trunk? Thanks, -Will [gcc] 2016-12-19 Will Schmidt * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling for early expansion of vector subtract builtins. [gcc/testsuite] 2016-12-19 Will Schmidt * gcc.target/powerpc/fold-vec-sub-char.c: New. * gcc.target/powerpc/fold-vec-sub-float.c: New. * gcc.target/powerpc/fold-vec-sub-floatdouble.c: New. * gcc.target/powerpc/fold-vec-sub-int.c: New. * gcc.target/powerpc/fold-vec-sub-int128.c: New. * gcc.target/powerpc/fold-vec-sub-longlong.c: New. * gcc.target/powerpc/fold-vec-sub-short.c: New. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index f0c1354..0ab8de3 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -16492,6 +16492,24 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) gsi_replace (gsi, g, true); return true; } + /* Flavors of vec_sub. We deliberately don't expand + P8V_BUILTIN_VSUBUQM. */ + case ALTIVEC_BUILTIN_VSUBUBM: + case ALTIVEC_BUILTIN_VSUBUHM: + case ALTIVEC_BUILTIN_VSUBUWM: + case P8V_BUILTIN_VSUBUDM: + case ALTIVEC_BUILTIN_VSUBFP: + case VSX_BUILTIN_XVSUBDP: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + gimple *g = gimple_build_assign (lhs, MINUS_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + default: break; } diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-char.c new file mode 100644 index 0000000..5063bd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-char.c @@ -0,0 +1,46 @@ +/* Verify that overloaded built-ins for vec_sub with char + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include + +vector signed char +test1 (vector bool char x, vector signed char y) +{ + return vec_sub (x, y); +} + +vector signed char +test2 (vector signed char x, vector bool char y) +{ + return vec_sub (x, y); +} + +vector signed char +test3 (vector signed char x, vector signed char y) +{ + return vec_sub (x, y); +} + +vector unsigned char +test4 (vector bool char x, vector unsigned char y) +{ + return vec_sub (x, y); +} + +vector unsigned char +test5 (vector unsigned char x, vector bool char y) +{ + return vec_sub (x, y); +} + +vector unsigned char +test6 (vector unsigned char x, vector unsigned char y) +{ + return vec_sub (x, y); +} + +/* { dg-final { scan-assembler-times "vsububm" 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-float.c new file mode 100644 index 0000000..8a29def --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-float.c @@ -0,0 +1,17 @@ +/* Verify that overloaded built-ins for vec_sub with float + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mno-vsx" } */ + +#include + +vector float +test1 (vector float x, vector float y) +{ + return vec_sub (x, y); +} + +/* { dg-final { scan-assembler-times "vsubfp" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-floatdouble.c new file mode 100644 index 0000000..c29acc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-floatdouble.c @@ -0,0 +1,23 @@ +/* Verify that overloaded built-ins for vec_sub with float and + double inputs for VSX produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -mvsx" } */ + +#include + +vector float +test1 (vector float x, vector float y) +{ + return vec_sub (x, y); +} + +vector double +test2 (vector double x, vector double y) +{ + return vec_sub (x, y); +} + +/* { dg-final { scan-assembler-times "xvsubsp" 1 } } */ +/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int.c new file mode 100644 index 0000000..1fac1dc --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int.c @@ -0,0 +1,47 @@ +/* Verify that overloaded built-ins for vec_sub with int + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include + +vector signed int +test1 (vector bool int x, vector signed int y) +{ + return vec_sub (x, y); +} + +vector signed int +test2 (vector signed int x, vector bool int y) +{ + return vec_sub (x, y); +} + +vector signed int +test3 (vector signed int x, vector signed int y) +{ + return vec_sub (x, y); +} + +vector unsigned int +test4 (vector bool int x, vector unsigned int y) +{ + return vec_sub (x, y); +} + +vector unsigned int +test5 (vector unsigned int x, vector bool int y) +{ + return vec_sub (x, y); +} + +vector unsigned int +test6 (vector unsigned int x, vector unsigned int y) +{ + return vec_sub (x, y); +} + +/* { dg-final { scan-assembler-times "vsubuwm" 6 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int128.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int128.c new file mode 100644 index 0000000..13caa9e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int128.c @@ -0,0 +1,24 @@ +/* Verify that overloaded built-ins for vec_sub with __int128 + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target int128 } */ +/* { dg-options "-maltivec -mvsx -mpower8-vector" } */ +/* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */ + +#include "altivec.h" + +vector signed __int128 +test1 (vector signed __int128 x, vector signed __int128 y) +{ + return vec_sub (x, y); +} + +vector unsigned __int128 +test2 (vector unsigned __int128 x, vector unsigned __int128 y) +{ + return vec_sub (x, y); +} + +/* { dg-final { scan-assembler-times "vsubuqm" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-longlong.c new file mode 100644 index 0000000..889fba4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-longlong.c @@ -0,0 +1,47 @@ +/* Verify that overloaded built-ins for vec_sub with long long + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-maltivec -mvsx -mpower8-vector" } */ + +#include + +vector signed long long +test1 (vector bool long long x, vector signed long long y) +{ + return vec_sub (x, y); +} + +vector signed long long +test2 (vector signed long long x, vector bool long long y) +{ + return vec_sub (x, y); +} + +vector signed long long +test3 (vector signed long long x, vector signed long long y) +{ + return vec_sub (x, y); +} + +vector unsigned long long +test4 (vector bool long long x, vector unsigned long long y) +{ + return vec_sub (x, y); +} + +vector unsigned long long +test5 (vector unsigned long long x, vector bool long long y) +{ + return vec_sub (x, y); +} + +vector unsigned long long +test6 (vector unsigned long long x, vector unsigned long long y) +{ + return vec_sub (x, y); +} + +/* { dg-final { scan-assembler-times "vsubudm" 6 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-short.c new file mode 100644 index 0000000..67052a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-short.c @@ -0,0 +1,47 @@ +/* Verify that overloaded built-ins for vec_sub with short + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include + +vector signed short +test1 (vector bool short x, vector signed short y) +{ + return vec_sub (x, y); +} + +vector signed short +test2 (vector signed short x, vector bool short y) +{ + return vec_sub (x, y); +} + +vector signed short +test3 (vector signed short x, vector signed short y) +{ + return vec_sub (x, y); +} + +vector unsigned short +test4 (vector bool short x, vector unsigned short y) +{ + return vec_sub (x, y); +} + +vector unsigned short +test5 (vector unsigned short x, vector bool short y) +{ + return vec_sub (x, y); +} + +vector unsigned short +test6 (vector unsigned short x, vector unsigned short y) +{ + return vec_sub (x, y); +} + +/* { dg-final { scan-assembler-times "vsubuhm" 6 } } */ +