| Message ID | 14815833.P6VixTcpEo@e108577-lin |
|---|---|
| State | New |
| Headers | show |
Ping? Best regards, Thomas On Friday 17 June 2016 18:21:44 Thomas Preudhomme wrote: > On Wednesday 01 June 2016 10:00:52 Ramana Radhakrishnan wrote: > > Please fix up the macros, post back and redo the test. Otherwise this > > is ok from a quick read. > > What about the updated patch in attachment? As for the original patch, I've > checked that code generation does not change for a number of combinations of > ISAs (ARM/Thumb), optimization levels (Os/O2), and architectures (armv4, > armv4t, armv5, armv5t, armv5te, armv6, armv6j, armv6k, armv6s-m, armv6kz, > armv6t2, armv6z, armv6zk, armv7, armv7-a, armv7e-m, armv7-m, armv7-r, > armv7ve, armv8-a, armv8-a+crc, iwmmxt and iwmmxt2). > > Note, I renumbered this patch 1a to not make the numbering of other patches > look strange. The CLZ part is now in patch 1b/7. > > ChangeLog entries are now as follow: > > > *** gcc/ChangeLog *** > > 2016-05-23 Thomas Preud'homme <thomas.preudhomme@arm.com> > > * config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM > to decide whether to prevent some libgcc routines being included for some > multilibs rather than __ARM_ARCH_6M__ and add comment to indicate the link > between this condition and the one in > libgcc/config/arm/lib1func.S. > > > *** gcc/testsuite/ChangeLog *** > > 2015-11-10 Thomas Preud'homme <thomas.preudhomme@arm.com> > > * lib/target-supports.exp (check_effective_target_arm_cortex_m): Use > __ARM_ARCH_ISA_ARM to test for Cortex-M devices. > > > *** libgcc/ChangeLog *** > > 2016-06-01 Thomas Preud'homme <thomas.preudhomme@arm.com> > > * config/arm/bpabi-v6m.S: Clarify what architectures is the > implementation suitable for. > * config/arm/lib1funcs.S (__prefer_thumb__): Define among other > cases for all Thumb-1 only targets. > (NOT_ISA_TARGET_32BIT): Define for Thumb-1 only targets. > (THUMB_LDIV0): Test for NOT_ISA_TARGET_32BIT rather than > __ARM_ARCH_6M__. > (EQUIV): Likewise. > (ARM_FUNC_ALIAS): Likewise. > (umodsi3): Add check to __ARM_ARCH_ISA_THUMB != 1 to guard the idiv > version. > (modsi3): Likewise. > (clzsi2): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__. > (clzdi2): Likewise. > (ctzsi2): Likewise. > (L_interwork_call_via_rX): Test for __ARM_ARCH_ISA_ARM rather than > __ARM_ARCH_6M__ in guard for checking whether it is defined. > (final includes): Test for NOT_ISA_TARGET_32BIT rather than > __ARM_ARCH_6M__ and add comment to indicate the connection between > this condition and the one in gcc/config/arm/elf.h. > * config/arm/libunwind.S: Test for __ARM_ARCH_ISA_THUMB and > __ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__. > * config/arm/t-softfp: Likewise. > > > Best regards, > > Thomas
Ping? Best regards, Thomas On Monday 27 June 2016 16:52:50 Thomas Preudhomme wrote: > Ping? > > Best regards, > > Thomas > > On Friday 17 June 2016 18:21:44 Thomas Preudhomme wrote: > > On Wednesday 01 June 2016 10:00:52 Ramana Radhakrishnan wrote: > > > Please fix up the macros, post back and redo the test. Otherwise this > > > is ok from a quick read. > > > > What about the updated patch in attachment? As for the original patch, > > I've > > checked that code generation does not change for a number of combinations > > of ISAs (ARM/Thumb), optimization levels (Os/O2), and architectures > > (armv4, armv4t, armv5, armv5t, armv5te, armv6, armv6j, armv6k, armv6s-m, > > armv6kz, armv6t2, armv6z, armv6zk, armv7, armv7-a, armv7e-m, armv7-m, > > armv7-r, armv7ve, armv8-a, armv8-a+crc, iwmmxt and iwmmxt2). > > > > Note, I renumbered this patch 1a to not make the numbering of other > > patches > > look strange. The CLZ part is now in patch 1b/7. > > > > ChangeLog entries are now as follow: > > > > > > *** gcc/ChangeLog *** > > > > 2016-05-23 Thomas Preud'homme <thomas.preudhomme@arm.com> > > > > * config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and > > __ARM_ARCH_ISA_ARM > > > > to decide whether to prevent some libgcc routines being included for some > > multilibs rather than __ARM_ARCH_6M__ and add comment to indicate the link > > between this condition and the one in > > > > libgcc/config/arm/lib1func.S. > > > > *** gcc/testsuite/ChangeLog *** > > > > 2015-11-10 Thomas Preud'homme <thomas.preudhomme@arm.com> > > > > * lib/target-supports.exp (check_effective_target_arm_cortex_m): > > Use > > > > __ARM_ARCH_ISA_ARM to test for Cortex-M devices. > > > > > > *** libgcc/ChangeLog *** > > > > 2016-06-01 Thomas Preud'homme <thomas.preudhomme@arm.com> > > > > * config/arm/bpabi-v6m.S: Clarify what architectures is the > > implementation suitable for. > > * config/arm/lib1funcs.S (__prefer_thumb__): Define among other > > > > cases for all Thumb-1 only targets. > > > > (NOT_ISA_TARGET_32BIT): Define for Thumb-1 only targets. > > (THUMB_LDIV0): Test for NOT_ISA_TARGET_32BIT rather than > > __ARM_ARCH_6M__. > > (EQUIV): Likewise. > > (ARM_FUNC_ALIAS): Likewise. > > (umodsi3): Add check to __ARM_ARCH_ISA_THUMB != 1 to guard the > > idiv > > version. > > (modsi3): Likewise. > > (clzsi2): Test for NOT_ISA_TARGET_32BIT rather than > > __ARM_ARCH_6M__. > > > > (clzdi2): Likewise. > > > > (ctzsi2): Likewise. > > (L_interwork_call_via_rX): Test for __ARM_ARCH_ISA_ARM rather than > > __ARM_ARCH_6M__ in guard for checking whether it is defined. > > (final includes): Test for NOT_ISA_TARGET_32BIT rather than > > __ARM_ARCH_6M__ and add comment to indicate the connection between > > this condition and the one in gcc/config/arm/elf.h. > > * config/arm/libunwind.S: Test for __ARM_ARCH_ISA_THUMB and > > __ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__. > > * config/arm/t-softfp: Likewise. > > > > Best regards, > > > > Thomas
On Fri, Jun 17, 2016 at 6:21 PM, Thomas Preudhomme <thomas.preudhomme@foss.arm.com> wrote: > On Wednesday 01 June 2016 10:00:52 Ramana Radhakrishnan wrote: >> Please fix up the macros, post back and redo the test. Otherwise this >> is ok from a quick read. > > What about the updated patch in attachment? As for the original patch, I've > checked that code generation does not change for a number of combinations of > ISAs (ARM/Thumb), optimization levels (Os/O2), and architectures (armv4, > armv4t, armv5, armv5t, armv5te, armv6, armv6j, armv6k, armv6s-m, armv6kz, > armv6t2, armv6z, armv6zk, armv7, armv7-a, armv7e-m, armv7-m, armv7-r, armv7ve, > armv8-a, armv8-a+crc, iwmmxt and iwmmxt2). > > Note, I renumbered this patch 1a to not make the numbering of other patches > look strange. The CLZ part is now in patch 1b/7. > > ChangeLog entries are now as follow: > > > *** gcc/ChangeLog *** > > 2016-05-23 Thomas Preud'homme <thomas.preudhomme@arm.com> > > * config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM to > decide whether to prevent some libgcc routines being included for some > multilibs rather than __ARM_ARCH_6M__ and add comment to indicate the > link between this condition and the one in > libgcc/config/arm/lib1func.S. > > > *** gcc/testsuite/ChangeLog *** > > 2015-11-10 Thomas Preud'homme <thomas.preudhomme@arm.com> > > * lib/target-supports.exp (check_effective_target_arm_cortex_m): Use > __ARM_ARCH_ISA_ARM to test for Cortex-M devices. > > > *** libgcc/ChangeLog *** > > 2016-06-01 Thomas Preud'homme <thomas.preudhomme@arm.com> > > * config/arm/bpabi-v6m.S: Clarify what architectures is the > implementation suitable for. > * config/arm/lib1funcs.S (__prefer_thumb__): Define among other cases > for all Thumb-1 only targets. > (NOT_ISA_TARGET_32BIT): Define for Thumb-1 only targets. > (THUMB_LDIV0): Test for NOT_ISA_TARGET_32BIT rather than > __ARM_ARCH_6M__. > (EQUIV): Likewise. > (ARM_FUNC_ALIAS): Likewise. > (umodsi3): Add check to __ARM_ARCH_ISA_THUMB != 1 to guard the idiv > version. > (modsi3): Likewise. > (clzsi2): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__. > (clzdi2): Likewise. > (ctzsi2): Likewise. > (L_interwork_call_via_rX): Test for __ARM_ARCH_ISA_ARM rather than > __ARM_ARCH_6M__ in guard for checking whether it is defined. > (final includes): Test for NOT_ISA_TARGET_32BIT rather than > __ARM_ARCH_6M__ and add comment to indicate the connection between > this condition and the one in gcc/config/arm/elf.h. > * config/arm/libunwind.S: Test for __ARM_ARCH_ISA_THUMB and > __ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__. > * config/arm/t-softfp: Likewise. > > > Best regards, > > Thomas OK - thanks for your patience and sorry about the delay. Ramana
diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h index 77f30554d5286bd83aeab0c8dc308cfd44e732dc..246de5492665ba2a0292736a9c53fbaaef184d72 100644 --- a/gcc/config/arm/elf.h +++ b/gcc/config/arm/elf.h @@ -148,8 +148,9 @@ while (0) /* Horrible hack: We want to prevent some libgcc routines being included - for some multilibs. */ -#ifndef __ARM_ARCH_6M__ + for some multilibs. The condition should match the one in + libgcc/config/arm/lib1funcs.S. */ +#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 #undef L_fixdfsi #undef L_fixunsdfsi #undef L_truncdfsf2 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 04ca17656f2f26dda710e8a0f9ca77dd963ab39b..38151375c29cd007f1cc34ead3aa495606224061 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3320,10 +3320,8 @@ proc check_effective_target_arm_cortex_m { } { return 0 } return [check_no_compiler_messages arm_cortex_m assembly { - #if !defined(__ARM_ARCH_7M__) \ - && !defined (__ARM_ARCH_7EM__) \ - && !defined (__ARM_ARCH_6M__) - #error !__ARM_ARCH_7M__ && !__ARM_ARCH_7EM__ && !__ARM_ARCH_6M__ + #if defined(__ARM_ARCH_ISA_ARM) + #error __ARM_ARCH_ISA_ARM is defined #endif int i; } "-mthumb"] diff --git a/libgcc/config/arm/bpabi-v6m.S b/libgcc/config/arm/bpabi-v6m.S index 5d35aa6afca224613c94cf923f8a2ee8dac949f2..27f33a4e8ced2cb2da8e38f5d78501954ee7363b 100644 --- a/libgcc/config/arm/bpabi-v6m.S +++ b/libgcc/config/arm/bpabi-v6m.S @@ -1,4 +1,5 @@ -/* Miscellaneous BPABI functions. ARMv6M implementation +/* Miscellaneous BPABI functions. Thumb-1 implementation, suitable for ARMv4T, + ARMv6-M and ARMv8-M Baseline like ISA variants. Copyright (C) 2006-2016 Free Software Foundation, Inc. Contributed by CodeSourcery. diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index 375a5135110895faa44267ebee045fd315515027..951dcda1c3bf7f323423a3e2813bdf0501653016 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -124,10 +124,14 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see && !defined(__thumb2__) \ && (!defined(__THUMB_INTERWORK__) \ || defined (__OPTIMIZE_SIZE__) \ - || defined(__ARM_ARCH_6M__))) + || !__ARM_ARCH_ISA_ARM)) # define __prefer_thumb__ #endif +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1 +#define NOT_ISA_TARGET_32BIT 1 +#endif + /* How to return from a function call depends on the architecture variant. */ #if (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__) @@ -305,7 +309,7 @@ LSYM(Lend_fde): #ifdef __ARM_EABI__ .macro THUMB_LDIV0 name signed -#if defined(__ARM_ARCH_6M__) +#ifdef NOT_ISA_TARGET_32BIT .ifc \signed, unsigned cmp r0, #0 beq 1f @@ -478,7 +482,7 @@ _L__\name: #else /* !(__INTERWORKING_STUBS__ || __thumb2__) */ -#ifdef __ARM_ARCH_6M__ +#ifdef NOT_ISA_TARGET_32BIT #define EQUIV .thumb_set #else .macro ARM_FUNC_START name sp_section= @@ -510,7 +514,7 @@ SYM (__\name): #endif .endm -#ifndef __ARM_ARCH_6M__ +#ifndef NOT_ISA_TARGET_32BIT .macro ARM_FUNC_ALIAS new old .globl SYM (__\new) EQUIV SYM (__\new), SYM (__\old) @@ -1054,7 +1058,7 @@ ARM_FUNC_START aeabi_uidivmod /* ------------------------------------------------------------------------ */ #ifdef L_umodsi3 -#ifdef __ARM_ARCH_EXT_IDIV__ +#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB != 1 ARM_FUNC_START umodsi3 @@ -1240,7 +1244,7 @@ ARM_FUNC_START aeabi_idivmod /* ------------------------------------------------------------------------ */ #ifdef L_modsi3 -#if defined(__ARM_ARCH_EXT_IDIV__) +#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB != 1 ARM_FUNC_START modsi3 @@ -1515,7 +1519,7 @@ LSYM(Lover12): #endif #ifdef L_clzsi2 -#if defined(__ARM_ARCH_6M__) +#ifdef NOT_ISA_TARGET_32BIT FUNC_START clzsi2 mov r1, #28 mov r3, #1 @@ -1576,7 +1580,7 @@ ARM_FUNC_START clzsi2 #ifdef L_clzdi2 #if !defined(HAVE_ARM_CLZ) -# if defined(__ARM_ARCH_6M__) +# ifdef NOT_ISA_TARGET_32BIT FUNC_START clzdi2 push {r4, lr} # else @@ -1601,7 +1605,7 @@ ARM_FUNC_START clzdi2 bl __clzsi2 # endif 2: -# if defined(__ARM_ARCH_6M__) +# ifdef NOT_ISA_TARGET_32BIT pop {r4, pc} # else RETLDM r4 @@ -1623,7 +1627,7 @@ ARM_FUNC_START clzdi2 #endif /* L_clzdi2 */ #ifdef L_ctzsi2 -#if defined(__ARM_ARCH_6M__) +#ifdef NOT_ISA_TARGET_32BIT FUNC_START ctzsi2 neg r1, r0 and r0, r0, r1 @@ -1738,7 +1742,7 @@ ARM_FUNC_START ctzsi2 /* Don't bother with the old interworking routines for Thumb-2. */ /* ??? Maybe only omit these on "m" variants. */ -#if !defined(__thumb2__) && !defined(__ARM_ARCH_6M__) +#if !defined(__thumb2__) && __ARM_ARCH_ISA_ARM #if defined L_interwork_call_via_rX @@ -1983,11 +1987,12 @@ LSYM(Lchange_\register): .endm #ifndef __symbian__ -#ifndef __ARM_ARCH_6M__ +/* The condition here must match the one in gcc/config/arm/elf.h. */ +#ifndef NOT_ISA_TARGET_32BIT #include "ieee754-df.S" #include "ieee754-sf.S" #include "bpabi.S" -#else /* __ARM_ARCH_6M__ */ +#else /* NOT_ISA_TARGET_32BIT */ #include "bpabi-v6m.S" -#endif /* __ARM_ARCH_6M__ */ +#endif /* NOT_ISA_TARGET_32BIT */ #endif /* !__symbian__ */ diff --git a/libgcc/config/arm/libunwind.S b/libgcc/config/arm/libunwind.S index a68b10ddce93d230c504f3747dcad3832d9f753c..3d7e70181fa80fe53a4903c96bb0f90480feee21 100644 --- a/libgcc/config/arm/libunwind.S +++ b/libgcc/config/arm/libunwind.S @@ -58,7 +58,7 @@ #endif #endif -#ifdef __ARM_ARCH_6M__ +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1 /* r0 points to a 16-word block. Upload these values to the actual core state. */ @@ -169,7 +169,7 @@ FUNC_START gnu_Unwind_Save_WMMXC UNPREFIX \name .endm -#else /* !__ARM_ARCH_6M__ */ +#else /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 */ /* r0 points to a 16-word block. Upload these values to the actual core state. */ @@ -351,7 +351,7 @@ ARM_FUNC_START gnu_Unwind_Save_WMMXC UNPREFIX \name .endm -#endif /* !__ARM_ARCH_6M__ */ +#endif /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 */ UNWIND_WRAPPER _Unwind_RaiseException 1 UNWIND_WRAPPER _Unwind_Resume 1 diff --git a/libgcc/config/arm/t-softfp b/libgcc/config/arm/t-softfp index 4ede438baf6a297737e52db00395f6c3a359f681..554ec9bc47b04445e79e84b1f957bf88680c08d1 100644 --- a/libgcc/config/arm/t-softfp +++ b/libgcc/config/arm/t-softfp @@ -1,2 +1,2 @@ -softfp_wrap_start := '\#ifdef __ARM_ARCH_6M__' +softfp_wrap_start := '\#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1' softfp_wrap_end := '\#endif'