From patchwork Wed Nov 16 10:18:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu X-Patchwork-Id: 695517 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tJgK03N52z9ryn for ; Wed, 16 Nov 2016 21:21:24 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Nf59XfTx"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=PpVH7NDRkoDs2x/D RGmHqeRWT7GSPUAGuiIaAIc/WdkNYntl6BDfensdMJGQmScbaUJB58UuQVAAB/73 Qe7WSxd5kb2ibJ1QkwcYIrDBoXwE6dAcww8QcrzO63gukAv9LZWQf1E6P1nxQqKc wCk98z9y07nbNgx+WPYTt++bpUw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=/cS6RUxOJK3algOZL77egz ZwwwU=; b=Nf59XfTxrNeYdMB+jyO0YpVnAd6i4ekOU7g+LndVBs0KtKXTLjYbPJ 8kiilxuZazBLvTyQdsE168z04GWqwcicORzb/izt0YMIH09BFzXDh6VAv+XN8iM4 UHxKAZWVHCQD+2JcPQed/C4mLwl+MzegksrZ1/qTFXeoiiCkq5noI= Received: (qmail 17950 invoked by alias); 16 Nov 2016 10:20:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 17893 invoked by uid 89); 16 Nov 2016 10:20:11 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_40, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=muhammad, ccc, rennecke, joernrenneckeembecosmcom X-HELO: smtprelay.synopsys.com Received: from smtprelay4.synopsys.com (HELO smtprelay.synopsys.com) (198.182.47.9) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 16 Nov 2016 10:20:00 +0000 Received: from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66]) by smtprelay.synopsys.com (Postfix) with ESMTP id B50E524E028D; Wed, 16 Nov 2016 02:19:59 -0800 (PST) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id A1DBE547; Wed, 16 Nov 2016 02:19:59 -0800 (PST) Received: from US01WXQAHTC1.internal.synopsys.com (us01wxqahtc1.internal.synopsys.com [10.12.238.230]) by mailhost.synopsys.com (Postfix) with ESMTP id 9784A546; Wed, 16 Nov 2016 02:19:59 -0800 (PST) Received: from IN01WEHTCA.internal.synopsys.com (10.144.199.104) by US01WXQAHTC1.internal.synopsys.com (10.12.238.230) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 16 Nov 2016 02:19:59 -0800 Received: from IN01WEHTCB.internal.synopsys.com (10.144.199.105) by IN01WEHTCA.internal.synopsys.com (10.144.199.103) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 16 Nov 2016 15:49:56 +0530 Received: from nl20droid1.internal.synopsys.com (10.100.24.228) by IN01WEHTCB.internal.synopsys.com (10.144.199.243) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 16 Nov 2016 15:49:56 +0530 From: Claudiu Zissulescu To: CC: , , Subject: [PATCH 3/4] [ARC] Refurbish mul64 support. Date: Wed, 16 Nov 2016 11:18:00 +0100 Message-ID: <1479291481-24225-4-git-send-email-claziss@synopsys.com> In-Reply-To: <1479291481-24225-1-git-send-email-claziss@synopsys.com> References: <1479291481-24225-1-git-send-email-claziss@synopsys.com> MIME-Version: 1.0 gcc/ 2016-07-04 Claudiu Zissulescu * config/arc/arc.md (mulsidi_600): Changed. (umulsidi_600): Likewise. (mul64): New pattern. (mulu64): Likewise. (mulsidi3): Changed. (umulsidi3): Likewise. --- gcc/config/arc/arc.md | 64 ++++++++++++++++++++++++++++++++------------------- 1 file changed, 40 insertions(+), 24 deletions(-) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 86de423..76a3207 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -12,10 +12,6 @@ ;; Profiling support and performance improvements by ;; Joern Rennecke (joern.rennecke@embecosm.com) ;; -;; Support for DSP multiply instructions and mul64 -;; instructions for ARC600; and improvements in flag setting -;; instructions by -;; Muhammad Khurram Riaz (Khurram.Riaz@arc.com) ;; This file is part of GCC. @@ -2011,14 +2007,26 @@ [(set_attr "is_sfunc" "yes") (set_attr "predicable" "yes")]) -(define_insn "mulsidi_600" +(define_insn_and_split "mulsidi_600" + [(set (match_operand:DI 0 "register_operand" "=c, c,c, c") + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%Rcq#q, c,c, c")) + (sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "Rcq#q,cL,L,C32")))) + (clobber (reg:DI MUL64_OUT_REG))] + "TARGET_MUL64_SET" + "#" + "TARGET_MUL64_SET" + [(const_int 0)] + "emit_insn (gen_mul64 (operands[1], operands[2])); + emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG)); + DONE;" + [(set_attr "type" "multi") + (set_attr "length" "8")]) + +(define_insn "mul64" [(set (reg:DI MUL64_OUT_REG) - (mult:DI (sign_extend:DI - (match_operand:SI 0 "register_operand" "%Rcq#q,c,c,c")) - (sign_extend:DI -; assembler issue for "I", see mulsi_600 -; (match_operand:SI 1 "register_operand" "Rcq#q,cL,I,Cal"))))] - (match_operand:SI 1 "register_operand" "Rcq#q,cL,L,C32"))))] + (mult:DI + (sign_extend:DI (match_operand:SI 0 "register_operand" "%Rcq#q, c,c, c")) + (sign_extend:DI (match_operand:SI 1 "nonmemory_operand" "Rcq#q,cL,L,C32"))))] "TARGET_MUL64_SET" "mul64%? \t0, %0, %1%&" [(set_attr "length" "*,4,4,8") @@ -2027,14 +2035,26 @@ (set_attr "predicable" "yes,yes,no,yes") (set_attr "cond" "canuse,canuse,canuse_limm,canuse")]) -(define_insn "umulsidi_600" +(define_insn_and_split "umulsidi_600" + [(set (match_operand:DI 0 "register_operand" "=c,c, c") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%c,c, c")) + (sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "cL,L,C32")))) + (clobber (reg:DI MUL64_OUT_REG))] + "TARGET_MUL64_SET" + "#" + "TARGET_MUL64_SET" + [(const_int 0)] + "emit_insn (gen_mulu64 (operands[1], operands[2])); + emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG)); + DONE;" + [(set_attr "type" "umulti") + (set_attr "length" "8")]) + +(define_insn "mulu64" [(set (reg:DI MUL64_OUT_REG) - (mult:DI (zero_extend:DI - (match_operand:SI 0 "register_operand" "%c,c,c")) - (sign_extend:DI -; assembler issue for "I", see mulsi_600 -; (match_operand:SI 1 "register_operand" "cL,I,Cal"))))] - (match_operand:SI 1 "register_operand" "cL,L,C32"))))] + (mult:DI + (zero_extend:DI (match_operand:SI 0 "register_operand" "%c,c,c")) + (zero_extend:DI (match_operand:SI 1 "nonmemory_operand" "cL,L,C32"))))] "TARGET_MUL64_SET" "mulu64%? \t0, %0, %1%&" [(set_attr "length" "4,4,8") @@ -2098,9 +2118,7 @@ } else if (TARGET_MUL64_SET) { - operands[2] = force_reg (SImode, operands[2]); - emit_insn (gen_mulsidi_600 (operands[1], operands[2])); - emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG)); + emit_insn (gen_mulsidi_600 (operands[0], operands[1], operands[2])); DONE; } else if (TARGET_MULMAC_32BY16_SET) @@ -2332,9 +2350,7 @@ } else if (TARGET_MUL64_SET) { - operands[2] = force_reg (SImode, operands[2]); - emit_insn (gen_umulsidi_600 (operands[1], operands[2])); - emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG)); + emit_insn (gen_umulsidi_600 (operands[0], operands[1], operands[2])); DONE; } else if (TARGET_MULMAC_32BY16_SET)