Message ID | 1479291481-24225-2-git-send-email-claziss@synopsys.com |
---|---|
State | New |
Headers | show |
Hi Andrew, Please ignore this patch for the time being. I would like to double check the add_n/sub_n patterns. Sorry for this detour, Claudiu > -----Original Message----- > From: Claudiu Zissulescu > Sent: Wednesday, November 16, 2016 11:18 AM > To: gcc-patches@gcc.gnu.org > Cc: Claudiu Zissulescu <claziss@synopsys.com>; > Francois.Bedard@synopsys.com; andrew.burgess@embecosm.com > Subject: [PATCH 1/4] [ARC] Various fixes. > > The ifconversion was failing because a move involving the lp_count was > not match by movsi_ne. This patch updates the constraints such that > movsi_ne will match. The failing test is dg-torture.exp=pr68955.c for > archs and without small data. > > gcc/ > 2016-07-11 Claudiu Zissulescu <claziss@synopsys.com> > > * config/arc/arc.h (REG_CLASS_NAMES): Reorder. > * config/arc/arc.md (*add_n): Change. > (*sub_n): Likewise. > (movsi_ne): Update constraint to Rac. > --- > gcc/config/arc/arc.h | 2 +- > gcc/config/arc/arc.md | 18 +++++++++--------- > 2 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h > index cd8b9f1..642bf73 100644 > --- a/gcc/config/arc/arc.h > +++ b/gcc/config/arc/arc.h > @@ -617,10 +617,10 @@ enum reg_class > "MPY_WRITABLE_CORE_REGS", \ > "WRITABLE_CORE_REGS", \ > "CHEAP_CORE_REGS", \ > + "ALL_CORE_REGS", \ > "R0R3_CD_REGS", \ > "R0R1_CD_REGS", \ > "AC16_H_REGS", \ > - "ALL_CORE_REGS", \ > "ALL_REGS" \ > } > > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index 5a7699f..217935c 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -2897,10 +2897,10 @@ > (set (match_dup 3) (match_dup 4))]) > > (define_insn "*add_n" > - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcw,W,W,w,w") > - (plus:SI (mult:SI (match_operand:SI 1 "register_operand" > "Rcqq,c,c,c,c,c") > - (match_operand:SI 2 "_2_4_8_operand" "")) > - (match_operand:SI 3 "nonmemory_operand" > "0,0,c,?Cal,?c,??Cal")))] > + [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcw,W, > W,w,w") > + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "Rcqq, c,c, > c,c,c") > + (match_operand:SI 2 "_2_4_8_operand" "")) > + (match_operand:SI 3 "nonmemory_operand" "0, > 0,c,Cal,c,Cal")))] > "" > "add%z2%? %0,%3,%1%&" > [(set_attr "type" "shift") > @@ -2912,9 +2912,9 @@ > ;; N.B. sub[123] has the operands of the MINUS in the opposite order from > ;; what synth_mult likes. > (define_insn "*sub_n" > - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w") > - (minus:SI (match_operand:SI 1 "nonmemory_operand" "0,c,?Cal") > - (mult:SI (match_operand:SI 2 "register_operand" "c,c,c") > + [(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w") > + (minus:SI (match_operand:SI 1 "nonmemory_operand" > "0,c,?Cal") > + (mult:SI (match_operand:SI 2 "register_operand" "w,w,w") > (match_operand:SI 3 "_2_4_8_operand" ""))))] > "" > "sub%z3%? %0,%1,%2" > @@ -3570,8 +3570,8 @@ > (define_insn "*movsi_ne" > [(cond_exec > (ne (match_operand:CC_Z 2 "cc_use_register" "Rcc, Rcc, Rcc,Rcc,Rcc") > (const_int 0)) > - (set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,Rcq#q,Rcq#q, > w,w") > - (match_operand:SI 1 "nonmemory_operand" "C_0, h, ?Cal, > Lc,?Cal")))] > + (set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,Rcq#q,Rcq#q, > w,w") > + (match_operand:SI 1 "nonmemory_operand" "C_0, h, > ?Cal,LRac,?Cal")))] > "" > "@ > * current_insn_predicate = 0; return \"sub%?.ne %0,%0,%0%&\"; > -- > 1.9.1
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index cd8b9f1..642bf73 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -617,10 +617,10 @@ enum reg_class "MPY_WRITABLE_CORE_REGS", \ "WRITABLE_CORE_REGS", \ "CHEAP_CORE_REGS", \ + "ALL_CORE_REGS", \ "R0R3_CD_REGS", \ "R0R1_CD_REGS", \ "AC16_H_REGS", \ - "ALL_CORE_REGS", \ "ALL_REGS" \ } diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 5a7699f..217935c 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -2897,10 +2897,10 @@ (set (match_dup 3) (match_dup 4))]) (define_insn "*add_n" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcw,W,W,w,w") - (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "Rcqq,c,c,c,c,c") - (match_operand:SI 2 "_2_4_8_operand" "")) - (match_operand:SI 3 "nonmemory_operand" "0,0,c,?Cal,?c,??Cal")))] + [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcw,W, W,w,w") + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "Rcqq, c,c, c,c,c") + (match_operand:SI 2 "_2_4_8_operand" "")) + (match_operand:SI 3 "nonmemory_operand" "0, 0,c,Cal,c,Cal")))] "" "add%z2%? %0,%3,%1%&" [(set_attr "type" "shift") @@ -2912,9 +2912,9 @@ ;; N.B. sub[123] has the operands of the MINUS in the opposite order from ;; what synth_mult likes. (define_insn "*sub_n" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w") - (minus:SI (match_operand:SI 1 "nonmemory_operand" "0,c,?Cal") - (mult:SI (match_operand:SI 2 "register_operand" "c,c,c") + [(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w") + (minus:SI (match_operand:SI 1 "nonmemory_operand" "0,c,?Cal") + (mult:SI (match_operand:SI 2 "register_operand" "w,w,w") (match_operand:SI 3 "_2_4_8_operand" ""))))] "" "sub%z3%? %0,%1,%2" @@ -3570,8 +3570,8 @@ (define_insn "*movsi_ne" [(cond_exec (ne (match_operand:CC_Z 2 "cc_use_register" "Rcc, Rcc, Rcc,Rcc,Rcc") (const_int 0)) - (set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,Rcq#q,Rcq#q, w,w") - (match_operand:SI 1 "nonmemory_operand" "C_0, h, ?Cal, Lc,?Cal")))] + (set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,Rcq#q,Rcq#q, w,w") + (match_operand:SI 1 "nonmemory_operand" "C_0, h, ?Cal,LRac,?Cal")))] "" "@ * current_insn_predicate = 0; return \"sub%?.ne %0,%0,%0%&\";